3D Semiconductor Memory via Etching Sub-Array Segmentation
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Solution Overview
Problem
Conventional three-dimensional resistive storage technology faces challenges in scaling and high-density integration due to the requirement of diodes or selection transistors, and the existing etching process struggles to achieve a suitable ratio between the depth and diameter of vias, limiting the number of layers that can be integrated in resistive cells.
Innovation Solution
A method for manufacturing a three-dimensional semiconductor memory device involves forming vertical ring-shape resistive cells with a shared bottom electrode, dividing the storage array into sub-arrays, and etching vias for each sub-array separately, allowing for flexible etching dimensions and reducing the complexity of the etching process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching process is used to form vias for multi-layer resistive cells, then the via depth-to-diameter ratio is limited, but the number of integrable layers is insufficient
Solution Approach 1:
The patent divides the storage array into multiple sub-arrays, where each sub-array has its own via structure. This segmentation allows the etching process to be applied to smaller, manageable via structures rather than attempting to etch one extremely deep via for the entire array, thereby achieving both sufficient depth-to-diameter ratio and high layer integration
Solution Approach 2:
The patent transitions from a single-column via structure to a multi-column via arrangement by dividing the array into sub-arrays. This dimensional change in the via layout enables the etching process to achieve adequate depth-to-diameter ratios while integrating more layers through the distributed sub-array architecture
2Reliability
If diodes or selection transistors are used in resistive cells, then cell selection is achieved, but device complexity increases
Solution Approach 1:
The patent extracts the cell selection function from the resistive cell structure itself and implements it through the transistor gate control mechanism. By separating the selection function (handled by transistor gating) from the storage function (handled by the resistive cell), the design achieves reliable cell selection without adding diodes or complex selection circuits within each cell
Solution Approach 2:
The transistor gate serves multiple functions: it acts as the word line for cell selection and simultaneously provides the control mechanism for the resistive cell operation. This multi-functionality eliminates the need for separate selection components, reducing device complexity while maintaining reliable cell selection capability
Data Source
AI summary
The present disclosure provides a method for manufacturing a three-dimensional semiconductor memory device. In the method, a storage array is divided into a plurality of storage sub-arrays. As a result, a respective via of each storage sub-array can be etched respectively, which is different from the prior art, where a via for a bottom electrode of a plurality of layers of resistive cells is etched at one time. The vias are filled with metal so that storage sub-arrays are connected with each other. The method for manufacturing the three-dimensional semiconductor memory device according to the present disclosure can substantially reduce process complexity and difficulty of etching process in high-density integration, and also improve a number of layers of the resistive cells integrated in the storage array.