Shared Bottom Electrode Contact for 3D Memory Capacitor Integration
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Solution Overview
Problem
Current semiconductor manufacturing processes for vertical three-dimensional (3D) memory devices face challenges in integrating periphery capacitors with array capacitors, leading to separate and time-consuming formation processes, which can increase processing time and complexity.
Innovation Solution
The integration of periphery capacitors with a common bottom electrode contact during the back end of line (BEOL) processing, allowing for simultaneous formation with array capacitors, reduces processing time and enhances operational efficiency by utilizing the same electrode for both periphery and array capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If periphery capacitors are formed separately from array capacitors, then periphery capacitor functionality is achieved, but processing time and manufacturing complexity increase
Solution Approach 1:
The patent merges the formation of periphery capacitors and array capacitors into a single integrated process. The bottom electrode contact serves as a common electrode for both periphery capacitors (formed in peripheral regions) and array capacitors (formed in memory array regions), eliminating the need for separate formation processes and reducing overall processing time
Solution Approach 2:
The bottom electrode contact structure is designed to serve multiple functions: it acts as the bottom electrode for array capacitors in the memory array regions and simultaneously serves as the bottom electrode for periphery capacitors in the peripheral circuit regions. This multi-functional design allows a single structure to support both capacitor types without requiring additional dedicated structures
2Reliability
If periphery capacitors are formed separately from array capacitors, then distinct capacitor structures are achieved, but device complexity and process steps increase
Solution Approach 1:
The patent combines the fabrication processes for periphery and array capacitors into a unified sequence. Both capacitor types share common process steps including forming the bottom electrode contact, depositing dielectric layers, and creating top electrodes, thereby reducing the total number of process steps and manufacturing complexity while maintaining distinct functional structures
3Productivity
If a common bottom electrode contact is used for periphery and array capacitors, then processing time is reduced, but electrode design complexity increases
Solution Approach 1:
The common bottom electrode contact is segmented into different functional regions: array regions where it serves array capacitors and peripheral regions where it serves periphery capacitors. This segmentation is achieved through selective patterning and etching processes that define different capacitor structures in different regions while using the same underlying electrode, thereby managing design complexity through regional differentiation
Data Source
AI summary
Systems, methods and apparatus are provided for an array of vertically stacked memory cells having a bottom electrode contact for an array of vertically stacked memory cells. The bottom electrode contact is formed in a periphery region. The bottom electrode contact is electrically coupled to a number of bottom electrodes of capacitors that are also formed in the periphery region.