Discrete 3D Processor Layout for High-Density Memory Computing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional processors, based on two-dimensional integration and von Neumann architecture, face limitations in computational density, computational complexity, and efficiency due to limited internal memory and the inability to effectively implement non-arithmetic functions, leading to inefficiencies in mathematical computing, computer simulation, pattern processing, and neural networks.
Innovation Solution
A discrete 3-D processor design that de-integrates 2-D and 3-D circuits, partitioning them into separate dice for optimized performance, featuring a plurality of storage-processing units with 3D-M arrays and processing circuits, allowing for increased computational density and flexibility by separating memory and processing components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional 2-D integration is used, then manufacturing simplicity is maintained, but computational density and internal memory capacity are limited
Solution Approach 1:
The patent transitions from conventional 2-D integration to 3-D integration by stacking multiple processing layers vertically. This dimensional change enables significantly increased computational density and internal memory capacity without proportionally increasing the chip footprint, directly resolving the contradiction between productivity and device complexity.
Solution Approach 2:
The patent implements nested structures where memory cells are positioned between word lines in a three-dimensional arrangement, and multiple functional layers are stacked within a single chip. This nesting approach maximizes the use of available space, enabling high computational density while maintaining manageable device complexity through systematic layering.
2Productivity
If von Neumann architecture is used, then physical separation of processor and memory is achieved, but data transfer bandwidth is limited
Solution Approach 1:
The patent merges the processor and memory into a unified 3-D integrated structure where memory cells and processing elements coexist on the same chip in close proximity. This merging eliminates the physical separation inherent in von Neumann architecture, enabling high-bandwidth data transfer through short interconnect distances while maintaining architectural complexity through modular 3-D organization.
Solution Approach 2:
By transitioning to 3-D integration, the patent creates multiple layers of memory and processing elements stacked vertically, enabling parallel data paths and significantly increased data transfer bandwidth. The third dimension provides additional routing pathways that overcome the bandwidth limitations of planar 2-D architectures.
3Productivity
If 3-D integration is implemented, then computational density increases, but manufacturing complexity and cost increase
Solution Approach 1:
The patent segments the 3-D integrated circuit into distinct functional layers (memory layers, processing layers, interconnect layers) that can be manufactured and tested separately before final assembly. This segmentation reduces manufacturing complexity by breaking down the complex 3-D fabrication process into manageable stages while maintaining high computational density through precise layer stacking.
4Productivity
If limited internal memory is used, then processor die size is reduced, but efficiency in mathematical computing decreases
Solution Approach 1:
The patent uses 3-D vertical stacking to increase internal memory capacity without proportionally increasing die area. By stacking memory layers vertically above the processing layer, the system achieves high computing efficiency through abundant on-chip memory while maintaining a compact processor die footprint.
Solution Approach 2:
The patent nests memory structures within the processor die by positioning memory cells between word lines and stacking multiple memory layers within the same chip footprint. This nesting approach provides large internal memory capacity for high computing efficiency while minimizing the overall die area through three-dimensional space utilization.
Data Source
AI summary
A discrete three-dimensional (3-D) processor comprises a plurality of storage-processing units (SPU's), each of the SPU's comprising a non-memory circuit, at least a memory array and at least an off-die peripheral-circuit component thereof. The 3-D processor further comprises first and second dice. The first die comprises the memory arrays, whereas the second die comprises the non-memory circuit and the off-die peripheral-circuit component.