3D Stacked SPAD Pixel Layout for Quench Circuit Miniaturization
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Solution Overview
Problem
Current SPAD pixels face challenges in miniaturization due to the complexity of miniaturizing the quench circuit, which limits the reduction in surface area.
Innovation Solution
A method of manufacturing SPAD pixels involving a stack of layers with molecular and hybrid bonding, where the SPAD is bonded to a quench circuit and a data processing circuit, allowing for the formation of distinct regions and interconnection networks to minimize surface area, with the quench circuit operating independently to manage the SPAD's avalanche.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the quench circuit is miniaturized to reduce surface area, then the surface area of the SPAD pixel is reduced, but the complexity of miniaturizing the quench circuit increases
Solution Approach 1:
The patent transitions from planar integration to three-dimensional stacking, placing the SPAD, quench circuit, and data processing circuit in separate vertical layers. This dimensional change allows each component to be optimized independently while achieving compact overall integration, effectively reducing surface area without proportionally increasing miniaturization complexity.
Solution Approach 2:
The patent divides the SPAD pixel into distinct functional segments: the SPAD layer, the quench circuit layer, and the data processing circuit layer. Each segment is independently designed and manufactured, then bonded together. This segmentation allows the quench circuit to be miniaturized using standard CMOS processes without directly constraining the SPAD design, resolving the contradiction between area reduction and miniaturization complexity.
2Reliability
If molecular bonding is used to bond the first level to the second level, then the bonding strength and alignment precision are improved, but the manufacturing process complexity increases
Solution Approach 1:
The patent incorporates alignment marks and bonding structures into the design before manufacturing begins. These preliminary features guide the molecular bonding process, ensuring precise alignment between layers without requiring complex real-time adjustment mechanisms. The alignment marks are fabricated during standard CMOS processing, so the additional complexity is minimal compared to the bonding reliability gains.
Solution Approach 2:
The patent uses insulating layers and bonding interfaces as intermediaries between the SPAD layer and quench circuit layer. These intermediary structures facilitate molecular bonding by providing compatible surfaces for bonding while maintaining electrical isolation. The intermediary layers are formed using standard deposition and etching processes, balancing manufacturing ease with bonding reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the miniaturization of SPAD pixels by optimizing the layout and bonding of components, effectively reducing the surface area while maintaining the functionality of the SPAD, quench, and data processing circuits.
Implementation Method 1
bonding, on the first level, by molecular bonding, a stack of layers comprising a semiconductor layer
Implementation Method 2
the second and third levels are bonded by hybrid bonding
Implementation Method 3
A photodiode is a semiconductor component having the ability of capturing a radiation in the optical domain and of transforming it into an electric signal
Implementation Method 4
SPADs are avalanche photodiodes operated above the breakdown voltage, and a photon reaching the multiplication region may alone start an avalanche and cause the breakdown of the junction
Data Source
AI summary
An electronic device includes a stack of a first level having a SPAD, a second level having a quench circuit for said SPAD, and a third level having a circuit for processing data generated by said SPAD. A method for making the device includes: a) forming of the first level; b) bonding, on the first level, by molecular bonding, of a stack of layers including a semiconductor layer; and c) forming the quench circuit of the second level in the semiconductor layer.


