Hybrid Memory Capacitor Stack for High Density and Low Parasitics
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing memory cell density and reducing parasitic capacitance, particularly in three-dimensional structures, which are essential for meeting demands for capacity and miniaturization in memory devices.
Innovation Solution
The semiconductor device incorporates a hybrid structure with ferroelectric and paraelectric capacitors stacked vertically, where ferroelectric capacitors have a flat plate shape and paraelectric capacitors have a cylindrical shape, allowing for increased integration and reduced parasitic capacitance by optimizing the arrangement of storage nodes and plate nodes, and sharing bit lines and word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically stacked memory cells are implemented to increase capacity, then memory cell density is improved, but parasitic capacitance increases
Solution Approach 1:
The patent segments the capacitor structure into distinct components: a first capacitor with ferroelectric material and a second capacitor with paraelectric material, stacked vertically. This segmentation allows each capacitor type to serve specific functions - the ferroelectric capacitor provides non-volatile storage while the paraelectric capacitor reduces parasitic effects, thereby increasing memory cell density without proportionally increasing parasitic capacitance.
Solution Approach 2:
The patent applies local quality by using different dielectric materials in different locations within the stacked capacitor structure. The ferroelectric material is used in the first capacitor where non-volatile storage is needed, while the paraelectric material is used in the second capacitor where reducing parasitic capacitance is prioritized. This localized material selection optimizes both density and parasitic capacitance characteristics.
2Area of stationary object
If three-dimensional stacked structure is used for miniaturization, then device area is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent implements a nested doll structure by vertically stacking the first capacitor containing ferroelectric material and the second capacitor containing paraelectric material within a shared footprint. This nesting approach allows multiple functional units to occupy the same lateral space, achieving miniaturization while the systematic stacking process manages manufacturing complexity through repeated patterning and deposition steps.
Solution Approach 2:
The patent transitions from two-dimensional lateral arrangement to three-dimensional vertical stacking, moving components into the vertical dimension. This dimensionality change enables higher integration density by utilizing the vertical space above existing structures, thereby reducing the device footprint while the standardized stacking process helps control manufacturing complexity.
3Duration of action of stationary object
If ferroelectric capacitors are used for non-volatile storage, then data retention is improved, but writing speed and durability are reduced
Solution Approach 1:
The patent merges ferroelectric and paraelectric capacitor technologies into a single hybrid memory device. The ferroelectric capacitor provides non-volatile data retention, while the paraelectric capacitor contributes faster write speeds and improved durability through its material properties. This combination allows the device to achieve both data retention and high-speed performance that neither material could provide alone.
Solution Approach 2:
The patent employs composite materials by integrating two different dielectric materials - ferroelectric and paraelectric - within the same memory device structure. This composite approach leverages the complementary strengths of each material: the ferroelectric material's non-volatile storage capability and the paraelectric material's fast switching and durability, thereby resolving the contradiction between data retention and writing speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances memory cell density and reduces parasitic capacitance, improving energy efficiency and data migration speed while compensating for the limitations of ferroelectric memory with the added durability and speed of dynamic random access memory.
Implementation Method 1
a first capacitor including a first plate node, a ferroelectric layer, and a first storage node coupled to the first plate node
Implementation Method 2
a second capacitor including a second plate node, a paraelectric layer, and a second storage node coupled to the second plate node
Data Source
AI summary
A semiconductor device includes: a first memory including first capacitors that are vertically stacked in a first direction; and a second memory that is laterally spaced apart from the first memory in a second direction and that includes second capacitors that are vertically stacked in the first direction. The first capacitors may include ferroelectric capacitors, and the second capacitors may include paraelectric capacitors.