Floating-Gate Memory Layout for Better Data Retention
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Solution Overview
Problem
Multi-time programmable (MTP) non-volatile semiconductor memory devices face challenges in maintaining excellent data retention characteristics due to the influence of electric charges from surrounding insulating layers, which affects the reliability and longevity of stored data.
Innovation Solution
The non-volatile semiconductor memory device incorporates a single-layer polysilicon gate structure with a specific configuration, including a semiconductor substrate, insulating layers, and conductive layers forming floating gates, where the fourth insulating layer is separated from the conductive layers to minimize the influence of electric charges, and a dummy gate and void structures are used to further enhance data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the fourth insulating layer is disposed close to the floating gates to reduce device area, then device integration density is improved, but data retention characteristics deteriorate due to electric charge influence from the insulating layer
Solution Approach 1:
A third insulating layer is introduced as an intermediary between the fourth insulating layer and the floating gates. This intermediate layer electrically shields the floating gates from electric charges in the fourth insulating layer, allowing the fourth layer to be positioned closer to the floating gates for improved integration density while maintaining data retention characteristics.
2Reliability
If multiple insulating layers are added to shield floating gates from electric charges, then data retention characteristics are improved, but device complexity increases
Solution Approach 1:
The third insulating layer is selectively formed only in regions where electric charge influence from the fourth insulating layer needs to be blocked, specifically between the fourth layer and the floating gates. This localized approach provides necessary shielding functionality while minimizing the overall structural complexity compared to forming insulating layers throughout the entire device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves data retention characteristics by reducing the impact of parasitic capacitance and electric charges, leading to longer storage retention times and enhanced reliability, while being compatible with CMOS processes for easy integration and manufacturing.
Implementation Method 1
a third insulating layer covering the first conductive layer and the second conductive layer... electric charges are held in each of the first conductive layer and the second conductive layer electrically insulated by separating the fourth insulating layer in distance from the first conductive layer and the second conductive layer
Data Source
AI summary
A non-volatile semiconductor memory device, includes: a semiconductor substrate; a first insulating layer disposed on the semiconductor substrate; a first conductive layer disposed on the first insulating layer and constituting a first floating gate of one of memory cells adjacent to each other; a second conductive layer disposed on the first insulating layer and constituting a second floating gate of the other one of the memory cells adjacent to each other; a third insulating layer covering the first conductive layer and the second conductive layer; and a fourth insulating layer disposed on the third insulating layer, wherein electric charges are held in each of the first conductive layer and the second conductive layer electrically insulated by separating the fourth insulating layer in distance from the first conductive layer and the second conductive layer.