C-Shaped MOSFET Gate Layout for RTS Noise Suppression
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Solution Overview
Problem
Random telegraph signal (RTS) noise, a type of low-frequency noise in MOSFET devices, reduces minimum operation voltage and signal-to-noise ratio in CMOS image sensors and flash memory, particularly exacerbated in smaller gate area MOSFETs, and is correlated with trapping sites at the interface between shallow trench isolation structures and MOSFET devices.
Innovation Solution
A semiconductor structure with a C-shaped gate structure and asymmetric source/drain regions is introduced, where the C-shaped gate confines currents away from trapping sites and increases current density on the source side to suppress RTS noise without violating design rule checking or requiring changes to manufacturing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOSFET gate area is reduced to increase integration density, then more components can be integrated into a given area, but RTS noise is exacerbated
Solution Approach 1:
The patent applies local quality by creating an asymmetric source/drain structure where the source region has a different geometry than the drain region. Specifically, the source region includes a source extension that extends beneath the gate structure, while the drain region has a different configuration. This local structural differentiation modifies the electric field distribution and current flow paths specifically in the source region, reducing RTS noise without affecting the overall device scaling.
Solution Approach 2:
The patent directly applies asymmetry by designing the source and drain regions with different geometries. The source region features a source extension that protrudes beneath the gate, creating an asymmetric configuration relative to the drain region. This asymmetric structure redistributes the electric field and current density, moving current paths away from the isolation structure interface where trapping sites are located, thereby mitigating RTS noise while maintaining scaled dimensions.
2Ease of manufacture
If conventional symmetric source/drain structures are used, then manufacturing is simpler, but RTS noise cannot be effectively suppressed
Solution Approach 1:
The patent intentionally breaks the symmetry of conventional source/drain structures by designing the source region with a source extension that extends beneath the gate structure, while the drain region maintains a different configuration. This asymmetric design is implemented through modified fabrication steps including selective epitaxial growth or ion implantation that create the asymmetric geometry. The asymmetry strategically positions current flow paths to avoid trapping sites at the isolation structure interface, effectively suppressing RTS noise while remaining compatible with existing manufacturing processes.
Data Source
AI summary
A semiconductor structure includes a gate structure, a source region, a drain region, and an isolation structure. The gate structure includes a first portion, a second portion and a third portion. The first portion extends in a first direction, and the second portion and the third portion extend in a second direction. The second portion and the third portion are disposed at opposite ends of the first portion. The source region and the drain region are separated by the gate structure. The isolation structure surrounds the gate structure, the source region and the drain region. The first portion has a first sidewall, the second portion has a second sidewall, and the third portion has a third sidewall. The first sidewall, the second sidewall and the third sidewall are parallel to the first direction and aligned with each other to form a straight line.