LED Chip Package Layout Without Wire Bonding
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Solution Overview
Problem
Existing LED display devices face challenges in miniaturization due to the space occupied by wire-bonding structures, and the flip-chip technique requires precise alignment and manufacturing, increasing costs.
Innovation Solution
A LED device design that includes a plurality of LED chips, an electric circuit layer assembly, and an encapsulating layer, where the electric circuit layer assembly is disposed on the second surfaces of the LED chips and the encapsulating layer encloses the LED chips and the electric circuit layer assembly, eliminating the need for wire bonding and reducing the device size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If wire-bonding structure is used to connect LED chips to electrodes, then electrical connection is achieved, but the device size increases due to space occupied by wire bonds
Solution Approach 1:
The patent extracts and eliminates the wire-bonding structure from the LED device. Instead of using separate wire bonds to connect LED chips to electrodes, the invention integrates the electrical connection function directly into the package substrate through conductive traces, removing the unnecessary wire-bonding components and reducing device size.
Solution Approach 2:
The patent merges the electrical connection function with the package substrate structure. The conductive traces are integrated into the package substrate itself, combining the substrate's mechanical support function with the electrical interconnection function, thereby eliminating the need for separate wire-bonding structures.
2Volume of moving object
If flip-chip technique is used to bond LED chips to conductive traces, then device size is reduced, but manufacturing cost increases due to precise alignment requirements
Solution Approach 1:
The patent applies preliminary action by pre-forming the conductive traces on the package substrate before mounting the LED chips. The conductive traces are prepared in advance with appropriate patterns and dimensions, and the LED chips are then bonded to these pre-prepared traces, simplifying the alignment process and reducing manufacturing complexity.
Solution Approach 2:
The patent changes the dimensional parameters of the conductive traces and LED chip mounting areas to optimize alignment tolerance. By carefully designing the trace dimensions, pad sizes, and spacing, the invention creates a mounting structure that is more tolerant to alignment variations, thereby reducing manufacturing cost.
Data Source
AI summary
A LED device includes multiple LED chips each including opposite first and second surfaces, a side surface, and an electrode assembly disposed on the second surface and including first and second electrodes. The first surface of each of the LED chips is a light exit surface. The LED device further includes an electric circuit layer assembly disposed on the second surfaces of the LED chips and having opposite first and second surfaces and a side surface. The first surface is electrically connected to the first and second electrodes. The LED device further includes an encapsulating layer enclosing the LED chips and the electric circuit layer assembly to expose the second surface of the electric circuit layer assembly.