All-Around Gate Semiconductor Device Bulk Wafer Process
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Solution Overview
Problem
Current methods for forming semiconductor devices with all-around gates often rely on costly silicon on insulator (SOI) structures and involve complex processes, necessitating a more cost-effective and efficient approach.
Innovation Solution
A method using a bulk wafer to form semiconductor devices with all-around gates by creating intermediate structures with selectively etchable fin portions, replacing sacrificial fin portions with dielectric material, and forming gates around the fin portions, eliminating the need for SOI structures and simplifying the process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon on insulator (SOI) structures are used to form all-around gate semiconductor devices, then device performance and all-around gate formation are achieved, but production cost increases
Solution Approach 1:
The patent extracts and removes the expensive SOI substrate requirement by using a bulk semiconductor wafer instead. The method forms all-around gates on bulk wafers through selective epitaxial growth and etching processes, eliminating the need for costly SOI structures while maintaining device performance.
Solution Approach 2:
The patent uses sacrificial fin portions made of selectively etchable material that are intentionally created and then removed to enable all-around gate formation. These temporary structures facilitate the manufacturing process and are discarded after serving their purpose, reducing overall production cost.
2Ease of manufacture
If conventional FinFET processes are used, then manufacturing simplicity is maintained, but all-around gate formation is not achieved
Solution Approach 1:
The patent segments the fin structure into two distinct portions: first fin portions that form the final device fins and second fin portions that serve as sacrificial elements. This segmentation allows selective processing where the second portions are removed to create all-around gates, transforming a simple planar process into one that produces complex three-dimensional gate structures.
Solution Approach 2:
The patent introduces an intermediate structure with selectively etchable second fin portions that acts as a mediator to achieve all-around gates. These intermediate sacrificial structures enable the transformation from conventional FinFET to nano-wire devices with all-around gates through controlled removal processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces production costs and simplifies the process of forming semiconductor devices with all-around gates, enabling the creation of nano-wire devices without the need for expensive SOI substrates while maintaining device performance.
Implementation Method 1
The plurality of second semiconductor fin portions may be selectively etchable with respect to the plurality of top first semiconductor fin portions
Data Source
AI summary
A method of making a semiconductor device includes forming an intermediate structure including second semiconductor fin portions above a first semiconductor layer, and top first semiconductor fin portions extending from respective ones of the second semiconductor fin portions. The second semiconductor fin portions are selectively etchable with respect to the top first semiconductor fin portions. A dummy gate is on the intermediate structure. The second semiconductor fin portions are selectively etched to define bottom openings under respective ones of the top first semiconductor fin portions. The bottom openings are filled with a dielectric material.