Variable-Width RF FET Stacks for Uniform Voltage Division
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Solution Overview
Problem
Voltage distribution across FETs in RF switch stacks is not uniform, leading to premature failure of the top FET and subsequent domino-like failure of other FETs, due to parasitic capacitances and neighboring stack interactions.
Innovation Solution
The solution involves designing the FET stack with varying widths, where the bottom FETs have increased widths and the top FETs have reduced widths, to optimize voltage distribution and capacitive compensation between neighboring stacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If FETs in a switch stack are made with uniform width, then manufacturing is simplified, but voltage distribution becomes non-uniform causing top FET failure
Solution Approach 1:
The patent applies local quality by making FET widths non-uniform within the stack, specifically reducing the width of upper FETs compared to lower FETs. This local variation in geometry compensates for the non-uniform voltage distribution caused by parasitic capacitances, ensuring that each FET operates within safe voltage limits while maintaining overall stack reliability.
2Reliability
If discrete capacitors are added for capacitive compensation, then voltage distribution improves, but device area and complexity increase
Solution Approach 1:
The patent implements self-service by using the FETs themselves to provide capacitive compensation through their inherent gate-to-source and gate-to-drain capacitances. By carefully selecting non-uniform width ratios, the FETs automatically compensate for voltage distribution non-uniformity without requiring external discrete capacitors, thereby reducing device area and complexity.
Solution Approach 2:
The patent applies parameter changes by modifying the width parameter of FETs in the stack. Specifically, it establishes width ratios where upper FETs have smaller widths than lower FETs, which changes the capacitive parameters of each FET to achieve uniform voltage distribution across the stack.
3Reliability
If FET width is reduced in upper positions, then voltage handling capacity decreases, but voltage distribution uniformity improves
Solution Approach 1:
The patent applies parameter changes by systematically varying FET widths according to specific ratios (e.g., W1:W2:W3 = 1:0.8:0.6 or 1:0.7:0.5) where upper FETs have reduced widths. This parameter optimization balances the trade-off between voltage handling capacity and voltage distribution uniformity, ensuring all FETs operate below their breakdown voltages.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures that all FETs operate below their breakdown voltage in both ON and OFF conditions of the neighboring stack, improving voltage handling and division while avoiding the need for additional capacitors, thus saving area, complexity, and cost.
Implementation Method 1
Such voltage distribution inequalities are generally caused by parasitic capacitances
Data Source
AI summary
Devices and methods to manufacture a stack of FET switches in presence of a neighboring stack of FET switches are described. The stack of FET switches is designed or manufactured so that at least its top FET has a width that is smaller than the width of its bottom FET. Other voltage handling configurations and distributions of widths are described.