Semiconductor Substrate Dynamic Frame Rate Control
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Solution Overview
Problem
Conventional display panels face challenges in reducing power consumption while maintaining display quality, as lowering the frame rate to reduce power consumption leads to increased leakage current and flickering issues, which are exacerbated by the need for larger storage capacitors that increase power hunger.
Innovation Solution
A semiconductor substrate with a specific configuration including data lines, scan lines, capacitance control lines, transistors, and storage capacitors, where the ON or OFF state of the second transistors is determined based on grayscale values and frame rates to optimize charging of storage capacitors, thereby reducing leakage current and flickering while saving power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the frame rate is lowered to reduce power consumption, then power consumption is reduced, but leakage current increases and flickering occurs
Solution Approach 1:
The patent implements dynamic frame rate adjustment based on display content characteristics. The system detects whether the displayed image contains moving objects or is static, and adaptively changes the frame rate accordingly - using higher frame rates for dynamic content to prevent flickering and lower frame rates for static content to save power. This dynamic adaptation resolves the contradiction by making frame rate a variable parameter rather than a fixed value.
Solution Approach 2:
The patent changes the frame rate parameter based on image characteristics analysis. By detecting motion in the displayed content and adjusting the frame rate parameter dynamically, the system optimizes the balance between power consumption and display quality. When motion is detected, frame rate increases to prevent flickering; when no motion is present, frame rate decreases to save power.
2Reliability
If storage capacitors are increased to reduce flickering, then flickering is ameliorated, but charging rate becomes insufficient and power consumption increases
Solution Approach 1:
The patent dynamically adjusts the storage capacitor value based on frame rate and display content. Instead of using a fixed large capacitor size, the system varies the capacitance according to whether the display content is static or dynamic. For static content at low frame rates, larger capacitance is used to maintain voltage and prevent flickering. For dynamic content, the system uses higher frame rates with smaller capacitance requirements, thereby reducing power consumption while still preventing flickering.
Solution Approach 2:
The patent performs preliminary detection of image characteristics before rendering to determine the appropriate frame rate and capacitor configuration. By analyzing the displayed content in advance and predicting potential flickering issues, the system can proactively adjust frame rate and capacitor settings before the flickering occurs, optimizing power consumption while preventing display artifacts.
3Reliability
If storage capacitors are increased to reduce flickering, then flickering is ameliorated, but the display panel becomes more power hungry
Solution Approach 1:
The patent implements dynamic adjustment of storage capacitor configuration based on display content and frame rate. The system uses larger effective capacitance only when necessary (at low frame rates with static content) and reduces capacitance requirements when frame rate is increased (for dynamic content). This dynamic approach reduces the overall power consumption of the display panel while maintaining flickering control when needed.
Data Source
AI summary
A semiconductor substrate including a data line, a scan line, a capacitance control line, a first transistor, a pixel electrode, a second transistor, a storage capacitor and a third transistor is provided. A first terminal of the first transistor is electrically connected to the data line. A control terminal of the first transistor is electrically connected to the scan line. The pixel electrode is electrically connected to a second terminal of the first transistor. A first terminal of the second transistor is electrically connected to the second terminal of the first transistor. A first terminal of the third transistor is electrically connected to the capacitance control line. A control terminal of the third transistor is electrically connected to the scan line, and a second terminal of the third transistor is electrically connected to a control terminal of the second transistor.