Array Substrate Fan-Out Layout for Uniform Sensing Capacitance
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Solution Overview
Problem
In glass-based Mini/Micro-Light Emitting Diode (MLED) direct display products, inconsistent capacitance of sensing lines leads to inaccurate detection and uneven image display due to variations in voltage and resistance, affecting the uniformity of LED light emission.
Innovation Solution
The array substrate design includes a pixel area with thin film transistors arranged in a multi-row and multi-column array, and a fan-out area with sub-fan-out areas connected by M1 traces of uniform transverse lengths, ensuring consistent contact areas and capacitances across different thin film transistors, thereby improving picture uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If sensing lines have different capacitance values, then the design flexibility is improved, but the detection accuracy and image uniformity deteriorate
Solution Approach 1:
The patent applies homogeneity by making all M1 traces have the same transverse length, ensuring uniform capacitance values across different sensing lines. This standardization eliminates detection accuracy issues while maintaining design flexibility through the overall trace layout configuration.
Solution Approach 2:
The patent changes the critical parameter of trace capacitance by controlling the transverse length of M1 traces to be identical. This parameter standardization ensures uniform electrical characteristics across all sensing lines, resolving the contradiction between design flexibility and detection precision.
2Adaptability or versatility
If M1 traces have different contact areas with other traces, then the routing flexibility is improved, but the capacitance consistency and picture uniformity deteriorate
Solution Approach 1:
The patent ensures homogeneity by standardizing the transverse length of all M1 traces, which directly controls the contact area with other traces. This uniformity guarantees consistent capacitance values and picture uniformity while allowing routing flexibility through the fan-out area layout.
3Manufacturing precision
If the transverse lengths of M1 traces are standardized, then the capacitance uniformity is improved, but the routing complexity increases
Solution Approach 1:
The patent segments the fan-out area into multiple sub-fan-out areas, each handling specific trace routing. This segmentation allows standardized M1 trace lengths within each segment while distributing the routing complexity across multiple organized sections, reducing overall system complexity.
Solution Approach 2:
The patent resolves routing complexity by utilizing the vertical dimension through multiple sub-fan-out areas arranged in different rows. This dimensional approach allows standardized horizontal trace lengths while accommodating vertical routing variations, effectively decoupling capacitance uniformity requirements from routing complexity.
Data Source
AI summary
The present disclosure provides an array substrate and a display panel containing the array substrate. The array substrate includes a pixel area and a fan-out area. The pixel area includes a plurality of thin film transistors arranged in a multi-row and multi-column array. The fan-out area includes a plurality of sub-fan-out areas, each of the plurality of sub-fan-out areas is arranged corresponding to a row of the plurality of thin film transistors, and each of the plurality of sub-fan-out areas is connected to a row of thin film transistors corresponding to the corresponding row of thin film transistors by a plurality of M1 traces. Wherein, transverse lengths of a portion of the plurality of M1 traces in at least one of the plurality of sub-fan-out areas are the same, so that a picture uniformity of the display panel can be improved.