Semiconductor Memory Control Circuit Layout Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor memory devices, the integration of control circuits below memory cell arrays is inefficient, leading to increased chip area and reduced space for minimizing necessary control circuits, which affects the overall performance and efficiency of memory storage.
Innovation Solution
The semiconductor memory device incorporates a word line driver and selection driver configuration with n-type and p-type MOSFETs connected in parallel, where the p-type MOSFETs are positioned below gaps between adjacent memory cell arrays, reducing the layout area of the selection driver and allowing for efficient voltage application to word lines and bit lines without increasing the word line driver's layout area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If control circuits are integrated below memory cell arrays, then chip area is reduced, but the layout area of control circuits increases due to inefficient integration
Solution Approach 1:
The control circuits are segmented into two types: first control circuits (word line drivers) disposed directly below memory cell arrays, and second control circuits (selection drivers) disposed below gaps between adjacent memory cell arrays. This segmentation allows efficient utilization of previously wasted space while maintaining functional separation and reducing overall chip area.
Solution Approach 2:
Different regions of the chip are assigned different functions based on their spatial characteristics. Memory cell array regions contain first control circuits for direct control, while gap regions contain second control circuits for selection functions. This local optimization ensures that each region contributes efficiently to the overall system functionality.
2Area of stationary object
If selection driver layout area is reduced, then chip area is minimized, but voltage application efficiency to bit lines may be compromised
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional vertical stacking. Control circuits are disposed in the vertical dimension below memory cell arrays and gaps, utilizing the third dimension (depth) to reduce planar layout area while maintaining electrical connection efficiency through vertical wiring structures.
Data Source
AI summary
A semiconductor memory device includes memory cell arrays that include a plurality of memory cells. A first control circuit with control transistors of a first conductivity type is in a first region below the memory cell arrays. A second control circuit includes a first transistor of a first conductivity type connected in parallel to a second transistor of a second conductivity type. One of the first and second transistors is connected to an end of at least one control transistor. The second control circuit delivers a voltage to the plurality of control transistors. The first transistor is disposed in the first region. The second transistor is disposed in a second region adjacent to the first region. The second region is below a gap between adjacent memory cell arrays.