3D Memory Match-Line Search for High-Density TCAM
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Solution Overview
Problem
Traditional memory devices face challenges in providing high-efficient storage density and flexible operations for content-addressable memory applications, particularly in implementing ternary content addressable memory (TCAM) functions.
Innovation Solution
A three-dimensional (3D) memory device with a memory array, controller, and match circuit that selects target memory cells and word lines sharing a global signal line for data search and match, precharges the global signal line, and outputs a match address based on voltage changes, enabling efficient data matching and flexible search operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional NOR flash memories are used to implement TCAM, then device characteristics are moderate, but storage density is low
Solution Approach 1:
The patent transitions from traditional 2D NOR flash memory architecture to a 3D vertical architecture. Memory cells are stacked in multiple layers along the vertical dimension, with word lines extending through multiple layers. This dimensional change enables significantly higher storage density while maintaining good device characteristics through the inherent structure of 3D flash memory technology.
2Quantity of substance
If 3D AND flash memories are used to implement TCAM, then storage density is high and device characteristics are good, but operational efficiency needs improvement
Solution Approach 1:
The patent segments the memory array into multiple banks, with each bank containing memory cells organized in layers. The controller can selectively activate specific banks and layers for search operations, enabling parallel processing of multiple search queries simultaneously. This segmentation strategy improves operational efficiency by dividing the large 3D memory space into manageable, independently operable units.
Solution Approach 2:
The patent implements precharging of global signal lines before search operations begin. Match lines are precharged to a predetermined voltage level in advance, and word lines are preselected based on the search key before the actual comparison operation. This preliminary action reduces the critical path delay during the actual search operation, thereby improving operational efficiency.
3Speed
If parallel search operations are implemented in TCAM, then searching speed is improved, but device complexity increases
Solution Approach 1:
The patent designs the 3D memory structure and controller to perform multiple functions: standard read operations, search operations with match line detection, and parallel processing of multiple search keys. The same memory cells and signal lines are utilized for different operational modes, reducing the need for dedicated hardware for each function and thereby controlling device complexity while enabling parallel search operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances storage density and operational efficiency by allowing parallel search and flexible data matching in TCAM operations, improving the performance of memory devices in high-speed searching applications.
Implementation Method 1
outputting a match address based on whether a voltage on the target global signal line is pulled down or not
Data Source
AI summary
A three-dimension (3D) memory device and an operation method thereof are provided. The 3D memory device includes: a memory array including a plurality of memory cells; a controller coupled to the memory array; and a match circuit coupled to memory array, wherein in data search and match, the controller selects from the memory cells a plurality of target memory cells sharing a same target global signal line, and the controller selects a plurality of target word lines sharing the target global signal line as a plurality of target search lines, wherein a search data sends to the target memory cells via the target search lines for data matching; the target global signal line is precharged; and outputting a match address based on whether a voltage on the target global signal line is pulled down or not.


