3D Memory Device Merge Pass Transistors
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Solution Overview
Problem
3-dimensional memory devices face challenges in reducing size due to the increased number of transistors required for controlling memory cells, leading to larger device sizes as the number of stacked memory cells increases.
Innovation Solution
A connection structure between transistors and memory cells, utilizing merge pass transistors to merge word lines and selection lines from multiple memory cell arrays, reducing the number of pass transistors and minimizing space, thereby reducing the overall size of the memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked memory cells is increased to achieve higher memory capacity, then the memory capacity is improved, but the number of transistors required for controlling the memory cells is dramatically increased, leading to increased device size
Solution Approach 1:
The patent merges control functions by sharing row decoders and pass transistors across multiple memory cell arrays. Specifically, a first row decoder controls both first and second memory cell arrays through shared pass transistors, reducing the total number of transistors required while maintaining the ability to independently address and control stacked memory cells for high memory capacity
Solution Approach 2:
The patent implements multi-functional transistors that serve multiple purposes. Pass transistors are designed to simultaneously control word lines across different memory cell arrays, and row decoders are configured to decode addresses for multiple stacked arrays, enabling a single component to perform multiple control functions and reduce overall device size
2Adaptability or versatility
If more transistors are added to control increased memory cells, then the control capability is improved, but the space required to arrange the transistors is increased
Solution Approach 1:
The patent combines multiple control functions into shared row decoder circuits that simultaneously manage word lines for first and second memory cell arrays. By merging the control paths and sharing pass transistor resources, the design achieves enhanced control capability for stacked memory cells without proportionally increasing the space required for transistor arrangement
Solution Approach 2:
The patent transitions from planar transistor arrangement to three-dimensional stacked memory cell configuration, where control transistors are positioned at the base level and manage vertically stacked memory arrays. This dimensional change allows control capability to scale with memory capacity while keeping the footprint area constant, as the memory cells extend in the vertical dimension rather than requiring additional horizontal space
Data Source
AI summary
A memory device including a first memory cell array including first memory cells stacked vertically on a first memory cell array region of a top surface of a substrate; a second memory cell array including second memory cells stacked vertically on a second memory cell array region of the top surface; first word lines coupled to the first memory cells and including a subset of first word lines and remaining first word lines; second word lines coupled to the second memory cells and including a subset of second word lines and remaining second word lines; and a row decoder, including a plurality of merge pass transistors each commonly connected to a respective one of the subset of first word lines and a respective one of the subset of second word lines, disposed in a region of the top surface between the first and second cell array regions.