Solid-State Devices TRIZ Cases

A conductive layer with insulating portions routes electrostatic discharge currents to a clamp device.

Segmented substrate regions with distinct crystal orientations enable high-frequency isolation for wide band gap devices integrated into SOI CMOS processes.

Local mending material seals breaches in the sealing layer of a thin-film device, preventing environmental corrosion and extending operational lifetime.

Selective removal of dummy fill metal patterns enables flat wafer surfaces for MTJ element formation.

A sacrificial layer in a dummy emission area absorbs hydrogen and moisture to protect the light emitting layer.

Local thinning of the interlayer insulating film mitigates Zara mura by reducing height differences between pixel electrode and overlapped areas.

Adjacent column pixels connect to distinct data lines via matrix electrodes, merging driver functions to lower manufacturing costs.

Low-temperature metal-induced crystallization prevents thermal damage to phase-change materials during resistive memory device fabrication.

A phosphor plate with a 20 to 70 percent protrusion area maintains structural integrity during polishing.

Segmenting the steering diode from the switching resistor decouples leakage control from data storage, enabling dense cross-point arrays.

A correlated electron switch uses a Mott transition to toggle impedance states without electroforming.

An in-cell touch panel integrates sensing electrodes with the display common electrode layer to reduce device thickness.

A stereoscopic display device uses a parallax barrier to spatially divide left-eye and right-eye images for 3D viewing.

Segmented heating zones and substrate rotation resolve contradictions between film uniformity and deposition rate in organic solar battery manufacturing.

A TFT array substrate uses a bent strip-like first electrode and a sheet-like second electrode with openings to reduce overlapping area.

An inorganic insulation layer sits between the planarized substrate and the bank structure to block moisture migration.

An array substrate combines sensing material with thin film transistors to form a large-area sensing layer on glass substrates.

A concave molded section transfers heat from integrated circuits to peripheral resin areas in semiconductor packages.

SnO glass powder absorbs laser radiation to lower softening points, preventing thermal degradation of active devices during sealing.

Adjacent light detecting mesa on same substrate converts emitted UV to electrical signals for real-time monitoring.

Segmented etching with sacrificial material increases stacked layers while maintaining channel continuity and read performance.

Curved lens surfaces redirect dispersed rays toward the normal direction, reducing lateral losses and boosting illumination intensity.

An excimer suppression group in platinum(II) emitters minimizes red-shift and enhances device efficiency by suppressing self-aggregation.

Blue pixel slit configuration adjusts opening distance to minimize oblique light reduction, correcting yellow shift without increasing manufacturing costs.

A thin film transistor uses a metal member over source and drain regions to lower contact resistance.

Merge pass transistors connect word lines across stacked memory cell arrays, reducing transistor count and device area.

A germanium light absorption apparatus uses a conformal passivation layer to protect etched sidewalls and reduce surface leakage current.

A multi-layered anti-reflective film uses convex and concave pyramid portions to totally reflect incident light back into the substrate.

An image sensor integrates red, green, blue, and infrared pixels with distinct optical filters to isolate signals.

Blending thermal imaging sub-pixels with display pixels on one substrate reduces device volume and weight while maintaining versatility.

A light-emitting device uses a stepped current diffusion layer to enable lateral charge movement.

A voltage regulator design uses stacked metal wires and conductive patterns to selectively activate connections for precise output voltage control.

A multi-portion programmable material structure uses damascene processing to pattern nested oxide layers for nonvolatile memory cells.

Inclined sidewall facets in wurtzite heteroepitaxial structures bend threading dislocations laterally, reducing defect density without thick buffer layers.

A maskless manufacturing method uses a light source to selectively irradiate substrate regions, preventing organic material deposition in non-deposition areas.

A light source device uses a high-reflectance top cover to reduce forward brightness and improve illumination evenness.

Common P-type and N-type doping regions merge four diodes into one substrate, reducing manufacturing complexity while maintaining rectifying function.

A ground-connected resistor on the word line pass limits current flow through thin dielectric layers in NAND flash memory arrays.

Segmented SrRuO3 and iridium oxide layers prevent lead diffusion while maintaining switching charge.

Remote plasma processing removes copper oxides and hydrocarbons from wafer interfaces while protecting low-k dielectrics from damage.

A doped hafnium oxide film with layered crystalline structures enhances ferroelectric properties at reduced thicknesses.

Selective etching removes sacrificial materials to form trenches and channel strings in vertically stacked memory arrays.

A resistive random access memory structure uses a coplanar protection layer and top electrode to ensure sidewall coverage.

A protection layer wraps conductive vias to prevent material migration during fabrication.

A multi-layered contact layer prevents volatile organic compound outgassing during metallization, ensuring reliable metal adhesion.

An optical member with alternating refractive index layers selectively reflects specific wavelengths to enhance transmittance in organic light-emitting displays.

Segmented adsorption and dynamic expansion components adapt to irregular cover plate shapes, eliminating interference during the bonding process.

A conductive etch-stop layer defines bit-line contact plug positions during semiconductor fabrication.

A cured leveling layer covers ink pattern edges on a base substrate, enabling thinner adhesive bonding that prevents air bubbles in flexible displays.