Vertical NAND Memory Stack Sequential Etching
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Solution Overview
Problem
The challenge in three-dimensional vertical NAND (VNAND) devices is the limited number of stacked memory layers due to hard mask thickness and reactive ion etching (RIE) energy constraints, which restricts the aspect ratio of memory openings and leads to channel discontinuity issues.
Innovation Solution
The solution involves forming memory stacks in multiple portions with separate etching steps, using thinner hard masks and landing pads to align memory openings, and incorporating built-in resistors to manage misalignment and increase the number of stacked layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked memory layers is increased, then storage capacity is improved, but the aspect ratio of memory openings increases leading to channel discontinuity
Solution Approach 1:
The memory stack is divided into multiple portions (first portion, second portion, third portion) that are formed separately. Memory openings are etched in sequential steps through each portion, allowing the total stack height to be increased without requiring a single excessively deep etch that would compromise channel continuity.
Solution Approach 2:
Sacrificial material is deposited in advance to fill portions of memory openings before the actual channel formation. This preliminary filling allows subsequent etching steps to proceed through the sacrificial material, ensuring continuous opening formation while building up additional stack layers.
2Quantity of substance
If the aspect ratio of memory openings is increased to accommodate more stacked layers, then storage capacity is improved, but read performance deteriorates due to increased resistance
Solution Approach 1:
The total stack is segmented into multiple portions formed in separate steps. Each portion contributes to the overall layer count without requiring the memory openings to traverse the entire height in a single continuous path, thereby reducing the effective aspect ratio and associated resistance.
Solution Approach 2:
Sacrificial material serves as an intermediary substance that facilitates the formation of continuous memory openings through multiple etching steps. By etching through sacrificial material layers between stack portions, the process maintains opening continuity while reducing the aspect ratio constraints.
3Manufacturing precision
If thinner hard masks are used to reduce aspect ratio, then manufacturing precision is improved, but alignment of memory openings becomes more difficult
Solution Approach 1:
The manufacturing process is segmented into multiple etching steps, each handling a portion of the total stack height. This allows the use of thinner hard masks for each individual etching step, improving the precision and control of memory opening formation while maintaining ease of manufacture through modular processing.
Data Source
AI summary
A method of making a vertical NAND device includes forming a lower portion of a memory stack over a substrate, forming a lower portion of memory openings in the lower portion of the memory stack, and at least partially filling the lower portion of the memory openings with a sacrificial material. The method also includes forming an upper portion of the memory stack over the lower portion of the memory stack and over the sacrificial material, forming an upper portion of the memory openings in the upper portion of the memory stack to expose the sacrificial material in the lower portion of the memory openings, removing the sacrificial material to connect the lower portion of the memory openings with a respective upper portion of the memory openings to form continuous memory openings, and forming a semiconductor channel in each continuous memory opening.