Bit-line Contact Plug Etch-stop Layer Alignment
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Solution Overview
Problem
Conventional methods for forming bit-line contact plugs in semiconductor processes suffer from misalignment errors, leading to damaged gate structure insulation and element failure, especially with narrower line widths.
Innovation Solution
A method where a conductive layer is formed as an etch-stop layer, allowing direct etching of the bit-line contact material layer to define plug positions, avoiding misalignment and protecting the gate structure insulation, and including a hard mask and dielectric layers for precise plug formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the conventional method of forming contact plugs by etching through BPSG layer after photoresist definition is used, then the process is simple and easy to manufacture, but alignment errors occur causing misaligned contact holes and damaged gate structure insulation
Solution Approach 1:
The conductive layer is formed as an etch-stop layer before the etching process to prevent misalignment damage. This preliminary protective action ensures that even if alignment errors occur during photoresist definition, the gate structure insulation remains protected by the conductive etch-stop layer, thereby improving contact plug alignment precision without significantly increasing process complexity
Solution Approach 2:
The conductive layer serves as an intermediary etch-stop layer between the photoresist-defined contact holes and the gate structure. This intermediary layer absorbs alignment errors and prevents direct damage to the gate structure, resolving the contradiction between manufacturing simplicity and alignment precision
2Length of moving object
If the line width is reduced to achieve narrower patterns, then the device scaling is improved, but alignment errors become more critical causing element failure
Solution Approach 1:
The conductive etch-stop layer is formed beforehand as a cushioning protective layer that absorbs alignment errors. This allows the use of narrower line widths for device scaling while maintaining element reliability, as the cushioning layer prevents alignment errors from causing catastrophic failures
3Manufacturing precision
If the conductive layer is formed as an etch-stop layer and direct etching of bit-line contact material layer is performed, then alignment precision is improved and gate structure insulation is protected, but additional process steps are required
Solution Approach 1:
The conductive layer serves multiple functions: it acts as both the bit-line contact material and the etch-stop layer. This multi-functionality improves contact plug position accuracy while minimizing the increase in process complexity, as the same layer performs dual roles rather than requiring separate dedicated layers
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents insulation damage and element failure by ensuring accurate contact plug placement and electrical connection, suitable for semiconductor processes with smaller critical dimensions, and maintains the integrity of the gate structure during manufacturing.
Implementation Method 1
forming a conductive layer, a bit-line contact material layer, and a hard mask layer on the substrate; and using the conductive layer as an etching stop layer to perform a first etching process to etch the hard mask layer and the bit-line contact material layer
Implementation Method 2
perform a first etching process to etch the hard mask layer and the bit-line contact material layer to form the bit-line contact plug on the source/drain
Implementation Method 3
forming a dielectric layer to completely cover the gate structure and the bit-line contact plug; and selectively removing the dielectric layer to expose the bit-line contact plug
Data Source
AI summary
A method for forming a bit-line contact plug includes providing a substrate including a transistor which includes a gate structure and a source/drain at both sides of the gate structure; forming a conductive layer, a bit-line contact material layer and a hard mask layer; performing an etching process using the conductive layer as an etching stop layer to etch the bit-line contact material layer and the hard mask layer and forming the bit-line contact plug on the source/drain. A transistor structure includes a gate structure and a source/drain at both sides of the gate structure, a conductive layer covering part of the gate structure and connected to the source/drain, and a bit-line contact plug disposed on the conductive layer and directly connected to the conductive layer.