Sacrificial Layer Etching for 3D Memory Array Isolation
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Solution Overview
Problem
Current memory array fabrication methods face challenges in efficiently forming vertically-stacked memory cells with precise control over sacrificial materials and etching processes, which affects the integrity and performance of memory cell structures.
Innovation Solution
The method involves forming a stack with vertically-alternating conductive and insulative tiers, using sacrificial materials of different compositions, and employing selective etching to create channel-material strings and trenches, followed by the deposition of conductive material to electrically couple channel material with the conductor tier, while also forming intervening material for lateral isolation between memory blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If sacrificial materials are used to define memory block regions and channel openings, then the structural integrity and precision of vertically-stacked memory cells are improved, but the process complexity and number of fabrication steps increase
Solution Approach 1:
Sacrificial materials are deposited and patterned in advance to define the three-dimensional memory block regions and channel openings before the actual memory cell structures are formed. This preliminary structuring enables precise spatial definition of where memory cells will be vertically stacked, ensuring manufacturing precision while allowing subsequent steps to proceed more efficiently
Solution Approach 2:
The sacrificial materials serve as intermediary structures that temporarily occupy the spaces where memory blocks and channel openings will eventually be formed. These intermediaries guide the formation of channel-material strings and are selectively removed to create the final memory array architecture, enabling complex 3D structures to be built with controlled precision
2Reliability
If selective etching processes are employed to remove sacrificial materials and form trenches, then the electrical isolation between memory blocks is improved, but the manufacturing complexity and process time increase
Solution Approach 1:
Different etching processes are applied to different regions of the substrate based on the local sacrificial material composition. First-tier sacrificial materials are removed with a first etching process, while second-tier sacrificial materials remain to define memory block regions. This localized selective removal achieves electrical isolation between memory blocks through trenches while preserving the structural definition provided by remaining sacrificial materials
Solution Approach 2:
The sacrificial material structure is segmented into multiple tiers with different compositions and removal timelines. The first-tier sacrificial materials are removed early to create trenches for electrical isolation, while second-tier sacrificial materials are retained longer to continue defining memory block regions. This segmentation allows isolation and structural definition to occur at different stages of the fabrication process
3Reliability
If conductive material is deposited to electrically couple channel material with conductor tier, then the electrical performance of memory cells is improved, but the manufacturing complexity increases
Solution Approach 1:
Conductive material is deposited in advance to form elevationally-extending connections between the conductor tier and the channel-material strings before the memory cell structures are fully formed. This preliminary conductive path establishment ensures reliable electrical coupling is built into the architecture from the outset, simplifying subsequent steps as memory cells are constructed around these pre-formed electrical connections
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of reliable memory cell strings with improved electrical coupling and isolation, enhancing the overall performance and reliability of the memory array.
Implementation Method 1
employing selective etching to create channel-material strings and trenches
Implementation Method 2
followed by the deposition of conductive material to electrically couple channel material with the conductor tier
Data Source
AI summary
A method used in forming a memory array comprising strings of memory cells comprises forming a lower portion of a stack, that will comprise vertically-alternating first tiers and second tiers, on a substrate. The stack comprises laterally-spaced memory-block regions. Material of the first tiers is of different composition from material of the second tiers. Horizontally-elongated lines are formed in a lowest first tier and that are individually between immediately-laterally-adjacent of the memory-block regions. The lines comprise sacrificial material of different composition from the first-tier material that is or will be formed above the lowest first tier and from the second-tier material that is or will be formed above the lowest first tier. The vertically-alternating first tiers and second tiers of an upper portion of the stack are formed above the lower portion and the lines. Channel-material strings are formed that extend through the first tiers and the second tiers in the upper portion to the lower portion. Horizontally-elongated trenches are formed into the stack that are individually between the immediately-laterally-adjacent memory-block regions and extend to the line there-between. The sacrificial material of the lines is removed through the trenches. Intervening material is formed in the trenches and void-spaces left as a result of the removing of the sacrificial material of the lines. Other embodiments are disclosed.