ESD Protection Floor Plan Design for Integrated Circuit Core
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Solution Overview
Problem
Integrated circuits are vulnerable to damage from electrostatic discharge (ESD) currents due to the inability to divert ESD currents away from the core circuit before they reach the clamp circuit, leading to potential damage.
Innovation Solution
A conductive layer with a specific floor plan design is implemented, featuring a first and second conductive portion with an insulating portion, electrically connected to a clamp device and the core circuit, ensuring that ESD currents are diverted to the clamp device rather than the core circuit, thereby preventing direct flow into the core.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a clamp circuit is disposed in the integrated circuit to clamp the ESD current, then the ESD current can be clamped, but the ESD current may flow into the core circuit before reaching the clamp circuit causing damage
Solution Approach 1:
The conductive layer is configured in advance with specific floor plan design to establish preferred current paths before ESD events occur. The insulating portion is strategically positioned to block direct current flow to the core circuit, while the conductive portions are arranged to guide ESD current toward the clamp circuit, ensuring that the current diversion mechanism is already in place and active before any ESD event occurs.
Solution Approach 2:
The conductive layer acts as an intermediary structure between the ESD event source and the core circuit. By designing the floor plan with specific conductive and insulating portions, it mediates the ESD current flow, redirecting it away from the vulnerable core circuit and toward the clamp circuit, thus protecting the core circuit without requiring direct modification of the clamp circuit itself.
2Reliability
If the ESD current is diverted to the clamp device, then the core circuit is protected from ESD damage, but the current capability and electromigration effects need to be enhanced
Solution Approach 1:
The floor plan design of the conductive layer optimizes geometric parameters such as the width, length, and arrangement of conductive portions to enhance current carrying capability. By adjusting these physical dimensions and configurations, the structure can handle higher ESD currents while minimizing electromigration effects, thus improving both protection effectiveness and current handling strength.
3Reliability
If the conductive layer is designed with floor plan configuration, then ESD current path is controlled, but parasitic capacitance needs to be minimized
Solution Approach 1:
The conductive layer employs local quality variations through strategic placement of insulating portions that create electric field shielding in specific areas. This local modification of the electric field distribution reduces parasitic capacitance formation between adjacent conductive elements, while maintaining effective current path control through the remaining conductive portions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively prevents ESD damage to the core circuit by preferentially routing ESD currents to the clamp device, enhancing current capability and reducing electromigration effects while minimizing parasitic capacitance.
Implementation Method 1
the first conductive portion is electrically connected between the conductive pad and the second conductive portion
Implementation Method 2
the insulating portion is surrounded by the first conductive portion and the second conductive portion
Data Source
AI summary
An electrostatic discharge protection (ESD) structure for protecting a core circuit of an integrated circuit from an ESD event received by a conductive pad of the integrated circuit is provided. The ESD protection structure includes a first conductive layer, a clamp device, a first electrical connection part and a second electrical connection part. The first conductive layer is formed below the conductive pad, and includes a first conductive portion, an insulating portion and a second conductive portion. The insulating portion is surrounded by the first conductive portion and the second conductive portion. The first conductive portion is electrically connected between the conductive pad and the second conductive portion. The clamp device is arranged for clamping the ESD event. The first electrical connection part is coupled between the first conductive portion and the clamp device. The second electrical connection part is coupled between the second conductive portion and the core circuit.