Wurtzite Heteroepitaxial Structures with Inclined Sidewall Facets
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Solution Overview
Problem
The integration of silicon-based devices with wurtzite semiconductor materials in semiconductor heterostructures is hindered by significant lattice and thermal expansion mismatches, leading to high defect densities in wurtzite thin films epitaxially grown on silicon substrates, which complicates the formation of functional semiconductor devices.
Innovation Solution
The use of wurtzite heteroepitaxial structures with inclined sidewall facets and lateral overgrowth techniques to control defect propagation, bending threading dislocations away from the c-axis and reducing defect density within the device layer, allowing for the formation of semiconductor devices with lower defect densities at thinner film thicknesses than traditional buffer layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thick buffer layers are used to reduce defect density, then device reliability is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent changes the crystallographic orientation parameter by growing wurtzite structures on inclined sidewall facets rather than vertical surfaces. This parameter change redirects defect propagation paths, allowing defect control without requiring thick buffer layers, thus resolving the contradiction between reliability and manufacturing complexity
Solution Approach 2:
The patent introduces a lateral dimension to defect control by using inclined sidewall facets that cause threading dislocations to propagate laterally rather than vertically. This dimensional change in defect propagation allows thin-film devices to achieve low defect densities without thick buffers, resolving the contradiction between reliability and device complexity
2Adaptability or versatility
If wurtzite materials are heteroepitaxially grown on silicon substrates, then integration with silicon CMOS is achieved, but defect density increases due to lattice and thermal expansion mismatches
Solution Approach 1:
The patent converts the harmful effect of lattice and thermal expansion mismatches into a beneficial defect redirection mechanism. The mismatches still generate threading dislocations, but the inclined sidewall facets cause these dislocations to propagate laterally along the facets rather than vertically through the device layer, transforming a harmful effect into a controlled defect management strategy that maintains silicon CMOS compatibility while achieving low defect densities
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of semiconductor devices with reduced defect densities, facilitating monolithic integration of III-N semiconductor devices with silicon-based MOSFETs and allowing for the creation of advanced semiconductor architectures with improved performance.
Implementation Method 1
bending threading dislocations away from the c-axis and reducing defect density within the device layer
Implementation Method 2
wurtzite heteroepitaxial structures with inclined sidewall facets for defect propagation control in silicon CMOS-compatible semiconductor devices
Data Source
AI summary
III-N semiconductor heterostructures including a raised III-N semiconductor structures with inclined sidewall facets are described. In embodiments, lateral epitaxial overgrowth favoring semi-polar inclined sidewall facets is employed to bend crystal defects from vertical propagation to horizontal propagation. In embodiments, arbitrarily large merged III-N semiconductor structures having low defect density surfaces may be overgrown from trenches exposing a (100) surface of a silicon substrate. III-N devices, such as III-N transistors, may be further formed on the raised III-N semiconductor structures while silicon-based transistors may be formed in other regions of the silicon substrate.