MRAM Logic Integration via Selective Dummy Fill Removal
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Solution Overview
Problem
The integration of magnetic random access memory (MRAM) devices with logic circuits is hindered by the need for uniform dummy fills over the entire wafer, which prevents seamless integration due to space constraints and potential defect-related issues when combining MRAM and CMOS elements.
Innovation Solution
A method is developed to remove dummy fill metal patterns over logic areas during MRAM fabrication, using dry etch or other methods, followed by planarization techniques like spin-on dielectric or CMP, allowing for the formation of flat surfaces and seamless integration of MTJ elements in both memory and logic areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If uniform dummy fill is applied over the entire wafer to create flat surfaces for MRAM fabrication, then the flatness required for optimal magnetic memory performance is achieved, but the integration with logic circuits is prevented due to space constraints and design constraints
Solution Approach 1:
The patent applies different treatments to different regions of the wafer: dummy fill is applied only in the memory area to achieve flatness, while the logic area remains free of dummy fill to allow circuit integration. This local differentiation resolves the contradiction between achieving uniform flatness and enabling logic circuit integration.
Solution Approach 2:
The wafer is segmented into distinct memory area and logic area regions. The dummy fill process is selectively applied only to the memory area, creating separate flat surfaces for MRAM fabrication without interfering with the logic circuit area, thus enabling both flatness requirements and circuit integration.
2Manufacturing precision
If dummy fill is applied over the logic area to achieve flat surfaces, then flat wafer surface is obtained for MRAM fabrication, but defect-related issues arise that prevent seamless integration with logic circuits
Solution Approach 1:
The patent applies dummy fill selectively only in the memory area where flatness is required for MRAM fabrication, while leaving the logic area without dummy fill. This local application eliminates defect-related issues in the logic area while maintaining the necessary flat surface in the memory area, thereby ensuring reliable integration.
3Adaptability or versatility
If dummy fill is removed from logic areas to enable integration, then seamless integration with logic circuits is achieved, but flat surfaces required for optimal MRAM performance are not obtained
Solution Approach 1:
The patent implements local quality by applying dummy fill exclusively to the memory area where flat surfaces are critical for MRAM performance, while leaving the logic area free of dummy fill to enable seamless circuit integration. This regional differentiation simultaneously achieves both integration capability and flat surface quality where needed.
Solution Approach 2:
The fabrication process is segmented into region-specific operations: dummy fill deposition is performed only on the memory area, followed by selective planarization that maintains flatness in the memory region while preserving the logic area for circuit integration without dummy fill interference.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the seamless integration of MRAM into logic circuits without design constraints, ensuring optimal performance and thermal stability, while avoiding defects related to the integration of MRAM and CMOS elements.
Implementation Method 1
a CMP process are required to fabricate such flat surfaces
Data Source
AI summary
A wafer has a memory area and a logic area and a topmost metal contact layer on the surface covered with dielectric and etch stop layers. In the memory area, vias are opened through the dielectric and etch stop layers to topmost metal contact layer. In the logic area, evenly distributed dummy fill patterns are opened through a portion of the dielectric and etch stop layers. These are filled with a metal layer and planarized, forming a flat wafer surface. MTJ elements in the memory area and dummy elements in the logic area are formed on the flat surface. The dummy MTJ elements and fill patterns are etched away in the logic area. Metal connections are formed to the topmost metal contact layer in the logic area and top lead connections to MTJ elements are formed in the memory area.