3D Memory Device Monocrystalline Channels Self-Aligned Bitlines
Solution Overview
Problem
Current 3D memory technologies face challenges with wire performance and power consumption due to the degradation of interconnects as transistors are scaled down, and existing 3D memory structures often use poly-silicon for memory cell channels, which suffer from higher cell-to-cell performance variations and lower drive capabilities compared to monocrystalline channels.
Innovation Solution
The development of multilayer 3D memory devices with monocrystalline channels using alternative methods beyond ion cut and successive layer transfers, incorporating self-aligned horizontal bit-lines and conductive memory control lines, and employing a structure with tunneling oxide regions and charge trap regions to enhance memory cell performance and reduce construction costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are scaled down to improve transistor performance and density, then transistor density improves, but wire performance degrades and power consumption increases
Solution Approach 1:
The patent transitions from planar 2D transistor arrangements to three-dimensional stacked architectures, enabling vertical stacking of multiple transistor layers. This dimensional change allows continued transistor density improvement without proportionally increasing wire lengths, as transistors are placed closer together in the vertical dimension while maintaining efficient interconnect routing within each layer.
2Ease of manufacture
If poly-silicon is used for memory cell channels to simplify manufacturing, then manufacturing ease improves, but cell-to-cell performance variations increase and drive capability decreases
Solution Approach 1:
The patent changes the material parameter from poly-silicon to monocrystalline silicon for the channel region. This parameter change fundamentally improves carrier mobility and reduces performance variations between cells, as monocrystalline silicon provides a more uniform and defect-free crystal structure compared to polycrystalline material, thereby enhancing drive capability and reliability.
3Speed
If existing 3D memory structures are used to reduce wire lengths, then wiring delay decreases, but construction costs increase due to complex fabrication processes
Solution Approach 1:
The patent segments the memory structure into multiple independently formable layers that can be stacked vertically. Each layer can be fabricated using standard planar processes, and the layers are subsequently stacked to form the 3D structure. This segmentation allows the benefits of reduced wire lengths to be achieved while maintaining compatibility with existing manufacturing processes, thereby controlling construction costs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables improved memory cell performance, reduced construction costs, and efficient memory control with independently controlled units, addressing the limitations of existing 3D memory technologies by utilizing monocrystalline channels and advanced lithography techniques.
Implementation Method 1
tunneling oxide regions
Implementation Method 2
charge trap regions
Data Source
AI summary
A 3D memory device, the device including: a first horizontal bit-line; a second horizontal bit-line disposed above the first horizontal bit-line, where the first horizontal bit-line and the second horizontal bit-line function as a source or a drain for a plurality of parallel vertically-oriented memory transistors, where the first horizontal bit-line and the second horizontal bit-line are self-aligned being formed following the same lithography step; and conductive memory control lines, where a first portion of the conductive memory control lines are disposed at least partially directly underneath the plurality of parallel vertically-oriented memory transistors, and where a second portion of the conductive memory control lines are disposed at least partially directly above the plurality of parallel vertically-oriented memory transistors.