Transistor TRIZ Cases

A segmented metal gate fill process forms distinct work function layers over FinFET fins to enable precise threshold voltage tuning.

Rare earth doped hafnium oxide gates stabilize the orthorhombic phase at low thermal budgets, enabling FeRAM arrays to endure over 10^8 polarization cycles.

A lateral gate electrode TFT switch uses vertically disposed source and drain electrodes to increase charging capacity.

Removing the access transistor from the antifuse structure resolves the contradiction between reliability and bit cell size in nanometer CMOS.

A multi-gate thin film transistor surrounds the active layer with a top gate side portion, preventing light-induced leakage current.

A bottom-gate thin-film transistor substrate design consolidates source electrode connections through a single contact hole to increase aperture ratio.

A junction-less gate-controlled voltage clamp device regulates power supply lines using field effect modulation.

Asymmetric spacer structures reduce parasitic Miller capacitance while maintaining low series resistance in scaled field effect transistors.

A graded AlGaN channel generates a 3DEG to spread charge and reduce electric fields in high electron mobility transistors.

A two-step etch process forms a gate recess in enhancement mode GaN transistors by sequentially removing cap and stressor layers.

Photolithography forms uniform sidewalls to resolve Iso/Dense loading effects and alignment deviations in NAND memory manufacturing.

Ion implantation introduces silicon or carbon impurities into germanium source and drain regions to induce lattice mismatch stress.

Spacers protect the high-resistance gate from silicide deposition, eliminating extra process steps while maintaining electrical reliability.

Segmented dielectric layers seal vertical channel openings, preventing conductive material intrusion into voids while increasing plug contact area.

A stacked semiconductor device reduces power consumption while increasing arithmetic processing speed.

A common current discharge path unifies heterogenic protection structures across multiple voltage domains.

A three-terminal snapback device uses a control circuit to dynamically adjust its voltage threshold for ESD events.

Tungsten liners prevent degradation of indium gallium zinc oxide channels by blocking harmful barrier material interactions.

Self-aligned junction isolation in stacked FinFET inverters resolves manufacturing precision limits while controlling device complexity.

A SONOS memory cell integrates with logic circuits using an ONO dielectric structure and deep N-well isolation.

Air gap spacers between annular gates lower parasitic capacitance in vertical gate-all-around memory structures.

Stacking an insulating oxide layer over the semiconductor channel reduces threshold voltage variation and off-current in oxide thin film transistors.

A fin field effect transistor fabrication method deposits a stress film over an exposed gate trench to create a strained channel region.

An isolation structure electrically separates high-voltage and low-voltage units in a semiconductor device.

Defected seed layers induce selective strain states in epitaxial transistor channels to enhance carrier mobility.

Protruding wirings with bent portions branch from power supply lines to connect semiconductor regions within standard cells.

Patterned high-k gate dielectric spacers enhance electron trapping in programmable memory devices.

A suspended gate non-volatile memory structure uses movable electrodes to isolate the storage node from the substrate.