Word Line Air Gap Structure Reduces Parasitic Capacitance in VGAA Memory
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Solution Overview
Problem
In vertical gate-all-around (VGAA) memory technologies, the close arrangement of semiconductor gates leads to increased parasitic capacitance and delay noise, negatively impacting device performance due to higher interference between adjacent gates.
Innovation Solution
A method is introduced to form a word line structure with a plurality of word line trenches and active area pillars, where insulating layers are formed, annular gates are created, and spacers are used to create an air gap structure between them, reducing parasitic capacitance and improving integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal annular gates are isolated by a silicon nitride layer in VGAA technology, then the word line structure can be formed, but parasitic capacitance between adjacent metal annular gates increases and device performance deteriorates
Solution Approach 1:
The patent extracts the harmful silicon nitride layer that causes parasitic capacitance and replaces it with an air gap structure. The air gap is created by removing the silicon nitride isolation layer between adjacent metal annular gates, thereby eliminating the source of parasitic capacitance while maintaining the structural integrity of the word line structure.
Solution Approach 2:
The patent changes the dielectric parameter between adjacent gates from silicon nitride (high permittivity) to air (low permittivity). This parameter change reduces the parasitic capacitance between adjacent metal annular gates, directly addressing the harmful effect while preserving the functional isolation required for device operation.
2Productivity
If arrangement density of semiconductors on substrate is increased, then integration density is improved, but distance between metal annular gates decreases and parasitic capacitance increases
Solution Approach 1:
The patent removes the silicon nitride isolation layer that contributes to parasitic capacitance, replacing it with air gaps. This extraction allows for reduced spacing between adjacent gates without increasing parasitic capacitance, thereby enabling higher integration density while maintaining electrical performance.
Solution Approach 2:
By changing the dielectric material from silicon nitride to air, the patent reduces the permittivity between adjacent gates. This parameter change allows gates to be placed closer together (increasing integration density) without proportionally increasing parasitic capacitance, as air has much lower dielectric constant than silicon nitride.
Data Source
AI summary
Embodiments provides a word line structure and a method for forming the same, and a semiconductor structure, relating to the field of memory technologies. The method for forming a word line structure includes: providing a base substrate including a substrate, and forming a plurality of word line trenches and a plurality of active area pillars arranged at intervals in the substrate; forming insulating layers on the plurality of active area pillars, and filling a first spacer between adjacent two of the insulating layers; processing each of the insulating layers, and forming an annular gate on the processed insulating layer; etching back the first spacer, such that a top of the first spacer is lower than a bottom of the annular gate; and depositing a second spacer at a top of the annular gate, and forming an air gap structure between the first spacer and the second spacer.