FinFET Gate Replacement with Segmented Metal Fill
Solution Overview
Problem
The semiconductor industry faces challenges in fabricating FinFET devices with high-k metal gate structures due to difficulties in threshold voltage tuning and etching high aspect ratio features, such as fins and gate electrodes, which result in gate current leakage and fin top damage during the manufacturing process.
Innovation Solution
The process involves forming high-k gate dielectric layers and work function adjustment layers over fins, using a gate replacement technology to replace dummy gates with metal gates, and employing redundant metal gate fill materials to prevent buildup on fins, thereby reducing gate current leakage and improving threshold voltage tuning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If gate replacement technology is used to form high-k metal gate structure, then threshold voltage tuning capability is improved, but gate current leakage occurs due to fin top damage
Solution Approach 1:
The gate electrode formation is segmented into multiple steps: first forming a metal layer over the high-k dielectric layer, then selectively removing portions of the metal layer to create gate electrodes with different work functions in different regions. This segmentation allows precise threshold voltage tuning while preventing gate current leakage through controlled metal distribution.
Solution Approach 2:
Different metal materials are used in different regions to achieve local optimization: a first metal material with first work function is used in a first region, and a second metal material with second work function is used in a second region. This local quality approach enables precise threshold voltage tuning for different device regions while preventing gate current leakage through appropriate material selection.
2Productivity
If high aspect ratio fins are etched to increase device density, then device density is improved, but etching difficulty increases due to high aspect ratio
Solution Approach 1:
The high-k gate dielectric layer and metal layer are formed over the fins before the gate electrode pattern is defined. This preliminary action allows the metal layers to conformally cover the high aspect ratio fin structures, making the subsequent gate electrode formation easier and reducing etching difficulty while maintaining high device density.
Solution Approach 2:
The high-k gate dielectric layer serves as an intermediary between the fin structure and the metal gate electrode. This intermediary layer protects the fin tops during processing and enables the formation of high aspect ratio fins with reduced etching difficulty while maintaining high device density.
3Reliability
If metal gate fill material is deposited to replace dummy gate, then metal gate structure is formed, but metal buildup on fins occurs causing fin top damage
Solution Approach 1:
Portions of the metal layer are selectively removed (taken out) after deposition to create the final gate electrode structure. This extraction process removes excess metal that would otherwise build up on fin tops and cause damage, while maintaining the necessary metal gate structure for reliable device operation.
Solution Approach 2:
The process is designed to prevent metal buildup on fins before it occurs by using selective deposition and removal steps. The preliminary anti-action is embedded in the multi-step gate electrode formation process that controls metal distribution, preventing fin top damage while forming the metal gate structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of semiconductor devices by minimizing gate current leakage and preventing fin top damage, while allowing for precise threshold voltage adjustment and improved manufacturing of high aspect ratio gate electrode layers.
Implementation Method 1
A high-k gate dielectric layer 122 is formed by depositing a high-k dielectric
Implementation Method 2
A first metal gate electrode fill material 70 is subsequently formed over the first and second fins
Data Source
AI summary
A semiconductor device manufacturing method includes forming fins in first and second regions defined on a substrate. The fins include first fin, second fin, third fin, and fourth fin. A dielectric layer is formed over fins and a work function adjustment layer is formed over dielectric layer. A hard mask is formed covering third and fourth fins. A first conductive material layer is formed over first fin and not over second fin. A second conductive material layer is formed over first and second fins. A first metal gate electrode fill material is formed over first and second fins. The hard mask covering third and fourth fins is removed. A third conductive material layer is formed over third fin and not over fourth fin. A fourth conductive material layer is formed over third and fourth fins, and a second metal gate electrode fill material is formed over third and fourth fins.