GaN FET Gate Recess via Two-Step Etch
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Solution Overview
Problem
The formation of a recessed gate in enhancement mode gallium nitride field effect transistors (GaN FETs) is challenging due to variations in etching time, which can result in defects in the barrier and stressor layers, and existing methods using etch-blocking layers are inefficient.
Innovation Solution
A semiconductor device with a two-step etch process is used to form a gate recess that extends through the cap and stressor layers but not the barrier layer, employing high temperature metal organic chemical vapor deposition (MOCVD) for the barrier layer, low temperature MOCVD for the stressor layer, and a two-step etch process involving a first etch to remove the cap layer and a second etch to remove the stressor layer, with anodic oxidation to facilitate the second etch step.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If timed etching is used to form the gate recess, then the etching process is simple, but the vertical separation from the low-doped GaN layer shows unacceptable variation
Solution Approach 1:
The etching process is divided into multiple sequential steps with different etchants, each targeting specific layers (cap layer, stressor layer, barrier layer) with different etch rates. This segmentation allows precise control over the gate recess depth and vertical separation from the low-doped GaN layer, eliminating the variation problem of single-step timed etching.
Solution Approach 2:
The patent changes the parameters of the etching process by using different etchants with selective etch rates for different layers. By controlling the duration and conditions of each etching step, the vertical separation is precisely controlled, transforming the process from a single-parameter (time) control to multi-parameter control for improved precision.
2Manufacturing precision
If etch-blocking layers are used to form the gate recess, then the vertical separation control is improved, but defects are introduced in the barrier layer and/or stressor layer
Solution Approach 1:
The patent removes the etch-blocking layer from the structure and replaces it with a selective chemical etching approach. By extracting the mechanical blocking function and replacing it with chemical selectivity, the method eliminates defects in the barrier and stressor layers while maintaining precise vertical separation control.
Solution Approach 2:
The patent introduces selectively etched layers (cap layer and stressor layer) as intermediaries that enable precise depth control without requiring etch-blocking layers. These intermediary layers are removed in controlled steps to achieve the desired gate recess depth, serving as a mediator between the etching process and the final structure.
3Device complexity
If a single etch process is used, then the manufacturing process is simple, but defects occur in the barrier layer and stressor layer
Solution Approach 1:
The etching process is segmented into multiple steps, each with specific etchants and duration parameters tailored to remove specific layers selectively. This segmentation prevents defects by controlling the etching depth at each stage, ensuring that the barrier and stressor layers are not damaged while achieving the required gate recess geometry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures precise control over the gate recess formation, reducing defects and variations, and enhances the reproducibility and performance of the GaN FETs by maintaining the integrity of the barrier layer while allowing for desired carrier densities and etch selectivity.
Implementation Method 1
with anodic oxidation to facilitate the second etch step
Implementation Method 2
forming the barrier layer with a high temperature metal organic chemical vapor deposition (MOCVD) process, forming the stressor layer with a low temperature MOCVD process and forming the cap layer with a low temperature MOCVD process
Data Source
AI summary
A semiconductor device containing an enhancement mode GaN FET on a III-N layer stack includes a low-doped GaN layer, a barrier layer including aluminum over the low-doped GaN layer, a stressor layer including indium over the barrier layer, and a cap layer including aluminum over the stressor layer. A gate recess extends through the cap layer and the stressor layer, but not through the barrier layer. The semiconductor device is formed by forming the barrier layer with a high temperature MOCVD process, forming the stressor layer with a low temperature MOCVD process and forming the cap layer with a low temperature MOCVD process. The gate recess is formed by a two-step etch process including a first etch step to remove the cap layer, and a second etch step to remove the stressor layer.