Asymmetric Spacer Structures for FET Parasitic Capacitance Reduction
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Solution Overview
Problem
As semiconductor devices shrink, they face issues such as increased short channel effects, edge effects like Miller capacitance, and punch through due to reduced channel length, which affect transistor performance and increase costs.
Innovation Solution
The formation of asymmetric spacer structures in field effect transistors (FETs) with varying thicknesses between and outside gate structures, allowing for differential source and drain extension lengths and overlaps, reducing parasitic capacitance and series resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the channel length of the FET is reduced to increase operating speed and device density, then the transistor operates faster and more devices can be produced per wafer, but short channel effects increase causing increased drain to source leakage current
Solution Approach 1:
The patent applies local quality by creating asymmetric spacer structures where the first spacer has a different thickness than the second spacer. This local differentiation allows the source and drain regions to have different overlap characteristics with the gate, enabling optimization of each side independently to reduce leakage while maintaining drive current.
Solution Approach 2:
The patent directly applies asymmetry by forming spacers with unequal thicknesses on opposite sides of the gate structure. The first spacer thickness is intentionally made different from the second spacer thickness, creating asymmetric source and drain extension regions that differentially control overlap capacitance and leakage current on each side of the transistor.
2Power
If the gate to source/drain extension overlap is increased to maintain drive current, then transistor drive current is maintained, but parasitic Miller capacitance increases adversely influencing transistor performance
Solution Approach 1:
The patent applies local quality by creating different overlap conditions at different locations. The asymmetric spacer structure ensures that one side of the gate has a larger overlap with the source/drain extension while the other side has a smaller overlap, allowing drive current to be maintained through the necessary overlap while minimizing Miller capacitance by reducing overlap on the critical side.
Solution Approach 2:
The patent uses asymmetry to differentially control the overlap between the gate and source/drain extensions on opposite sides. By making the spacers asymmetric, the patent creates unequal overlap regions that allow optimization of drive current on one side while minimizing parasitic capacitance on the other side where it is most harmful.
3Productivity
If the channel length is reduced to increase device density, then more transistors can be produced per wafer lowering cost, but edge effects become more severe
Solution Approach 1:
The patent applies local quality by creating asymmetric spacer structures that provide different local characteristics at the source and drain edges of the channel. This local differentiation helps mitigate edge effects by optimizing the electric field distribution and depletion region characteristics at each edge independently, allowing shorter channel lengths to be used without severe edge effect penalties.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maintains low series resistance while minimizing adverse effects like short channel effects and parasitic capacitance, enhancing transistor performance and density without increasing costs.
Implementation Method 1
The spacer layer is etched so as to form asymmetric spacer structures for the pair of adjacently spaced gate structures
Implementation Method 2
the substrate is implanted with doped regions having asymmetric characteristics in accordance with the asymmetric spacer structures
Data Source
AI summary
A method for forming asymmetric spacer structures for a semiconductor device includes forming a spacer layer over at least a pair of adjacently spaced gate structures disposed over a semiconductor substrate. The gate structures are spaced such that the spacer layer is formed at a first thickness in a region between the gate structures and at a second thickness elsewhere, the second thickness being greater than said first thickness. The spacer layer is etched so as to form asymmetric spacer structures for the pair of adjacently spaced gate structures.