Strain Control in Epitaxial Transistor Channels via Defected Seed Layers

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Solution Overview

Problem

Existing transistor architectures in CMOS ICs face challenges in selectively introducing channel strain, as benefits are polarity-dependent, requiring different materials and encapsulants for PMOS and NMOS transistors, leading to manufacturing complexities and non-planar device layers.

Innovation Solution

Incorporating defected regions into the sub-channel material of stratified fin structures to selectively control the strain state of the channel material, allowing a single channel material to be used for both polarities, with strain relief achieved through dopant implantation, enabling pseudomorphic or metamorphic states for enhanced carrier mobility.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If different channel materials are used for PMOS and NMOS transistors to achieve selective strain, then carrier mobility is improved, but device complexity and manufacturing complexity increase

Engineering Contradiction:
Improvecarrier mobilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by introducing defected regions selectively into the sub-channel material of specific fin structures. This creates localized strain relief in targeted areas (e.g., PMOS regions) while leaving other areas (e.g., NMOS regions) with full strain, allowing different strain states in different locations using the same channel material.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the physical-chemical state of the sub-channel material by introducing defected regions through dopant implantation. This alters the strain state parameter of the channel material from fully strained to partially relieved, enabling selective strain control without changing the channel material composition.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If different channel encapsulants are used for PMOS and NMOS transistors to achieve selective strain, then carrier mobility is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvecarrier mobilityVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent applies local quality by selectively forming defected regions in the sub-channel material of specific fin structures using selective dopant implantation. This creates localized strain relief without requiring different encapsulant materials, simplifying the manufacturing process while achieving selective strain for different transistor polarities.

Inventive Principle:
Principle #3Local quality

3Reliability

If defected regions are incorporated into sub-channel material to relieve strain, then carrier mobility is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improvecarrier mobilityVSAvoidmanufacturing precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by forming the defected regions in the sub-channel material before forming the channel material. This preliminary strain relief action allows the channel material to be deposited with controlled strain states without requiring precise control during subsequent processing steps.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses the sub-channel material as an intermediary layer between the substrate and the channel material. By introducing defected regions in this intermediary layer, strain is selectively relieved without directly affecting the channel material quality, reducing precision requirements for channel material formation.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for higher carrier mobility in both PMOS and NMOS transistors using a single channel material, reducing manufacturing complexity and maintaining a planar device layer, while selectively adjusting strain states to optimize performance.

Implementation Method 1

relaxing strain in the channel material of at least a first of the fin structures by implanting an impurity into the sub-channel material

Methodology Applied
Scientific EffectStrain relief: Stress Relaxation

Implementation Method 2

relaxing strain in the channel material of at least a first of the fin structures by implanting an impurity into the sub-channel material

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Implementation Method 3

an epitaxial layer of semiconductor material over a seed material, the epitaxial layer strained to accommodate a lattice parameter of the seed material

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS11495683B2Multiple strain states in epitaxial transistor channel through the incorporation of stress-relief defects within an underlying seed material
Publication Date: 2022.11.08 INTEL CORP
  • US11495683B2 patent drawing
  • US11495683B2 patent drawing
  • US11495683B2 patent drawing

AI summary

Multiple strain states in epitaxial transistor channel material may be achieved through the incorporation of stress-relief defects within a seed material. Selective application of strain may improve channel mobility of one carrier type without hindering channel mobility of the other carrier type. A transistor structure may have a heteroepitaxial fin including a first layer of crystalline material directly on a second layer of crystalline material. Within the second layer, a number of defected regions of a threshold minimum dimension are present, which induces the first layer of crystalline material to relax into a lower-strain state. The defected regions may be introduced selectively, for example a through a masked impurity implantation, so that the defected regions may be absent in some transistor structures where a higher-strain state in the first layer of crystalline material is desired.