Bottom-Gate TFT Substrate Single Contact Hole Aperture Ratio
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Solution Overview
Problem
Conventional thin-film transistor substrates with top-gate structures require at least two contact holes for connecting data lines with pixels, which is undesirable for high-resolution displays due to low aperture ratios and increased manufacturing complexity.
Innovation Solution
A thin-film transistor substrate design that includes a base substrate with a data line, source electrode, drain electrode, channel, and pixel electrode in the same layer, allowing for a single contact hole per pixel, and using metal oxides like zinc oxide or indium gallium zinc oxide, with a light-blocking pattern and passivation layer to enhance image quality and simplify manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If at least two contact holes are used for connecting data line with pixel in top-gate structure, then electrical connection is achieved, but aperture ratio decreases and manufacturing complexity increases
Solution Approach 1:
The patent transitions from a conventional top-gate structure to a bottom-gate structure, fundamentally changing the vertical arrangement of layers. This dimensional reorganization allows the source electrode to directly contact the data line through a single contact hole, eliminating the need for multiple contact holes while maintaining electrical connectivity and significantly increasing the aperture ratio.
Solution Approach 2:
The patent inverts the conventional gate structure by placing the gate electrode at the bottom instead of at the top. This inversion of the gating mechanism enables the source electrode to be positioned such that it can directly contact the data line, reducing the number of contact holes from two to one and thereby increasing the aperture ratio.
2Reliability
If at least two contact holes are used for connecting data line with pixel, then electrical connection is achieved, but manufacturing complexity and time increase
Solution Approach 1:
By changing from top-gate to bottom-gate structure, the patent reduces the number of contact holes required from two to one. This structural change simplifies the manufacturing process, reducing the number of patterning and etching steps needed, thereby decreasing manufacturing time and complexity while maintaining reliable electrical connection.
Solution Approach 2:
The patent merges the functions of multiple contact holes into a single contact hole by repositioning the source electrode to directly contact the data line. This consolidation reduces the number of separate manufacturing steps required for creating and filling multiple contact holes, thereby simplifying the overall manufacturing process and reducing production time.
3Reliability
If at least two contact holes are used for connecting data line with pixel, then electrical connection is achieved, but device complexity increases
Solution Approach 1:
The patent resolves the contradiction by fundamentally changing the vertical stacking order from top-gate to bottom-gate structure. This dimensional reorganization simplifies the device architecture by eliminating the need for multiple contact holes penetrating through intermediate layers, thereby reducing structural complexity while maintaining necessary electrical connections.
Solution Approach 2:
The patent extracts and eliminates the unnecessary intermediate contact hole from the conventional structure. By directly contacting the source electrode with the data line through a single contact hole in the bottom-gate configuration, the patent removes the redundant contact structure, thereby simplifying the overall device architecture.
Data Source
AI summary
A thin film transistor substrate includes the following elements: a base substrate, a data line disposed on the base substrate, a source electrode contacting the data line, a drain electrode spaced from the source electrode, a channel disposed between the source electrode and the drain electrode, a pixel electrode electrically connected to the drain electrode, a gate insulation pattern disposed on the channel, and a gate electrode disposed on the gate insulation pattern.