SONOS Memory Cell Integration in Logic Process
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Solution Overview
Problem
Integrating non-volatile memory cells with logic circuits on a chip is challenging due to compatibility issues with existing logic processes, which require additional processing steps and increase manufacturing costs, especially when high voltage transistors are needed for memory operations.
Innovation Solution
A non-volatile memory cell is fabricated using a modified single-poly logic process with an Oxide-Nitride-Oxide (ONO) dielectric structure and deep N-well or P-well isolation, allowing for electrically programmable and erasable memory cells that operate within the voltage limits of common logic transistors, using techniques like Fowler-Nordheim tunneling and Band-to-band hot-hole injection for programming and erasing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If specialized processes are used for non-volatile memory fabrication, then memory performance and functionality are improved, but manufacturing cost increases and compatibility with logic processes deteriorates
Solution Approach 1:
The patent implements a dual-gate transistor structure where the first gate controls logic operations and the second gate enables memory operations. This universal structure allows the same transistor to function as both a logic transistor and a memory transistor, eliminating the need for separate specialized memory fabrication processes and achieving compatibility with standard logic manufacturing while maintaining memory functionality.
2Reliability
If additional processing steps are added to logic process for memory integration, then non-volatile memory functionality is achieved, but manufacturing cost increases
Solution Approach 1:
The patent merges the formation of the second gate with the existing source and drain region formation steps in the logic process. By combining these operations into a single processing sequence, the patent achieves non-volatile memory functionality without requiring separate additional processing steps, thereby minimizing manufacturing cost increases.
3Reliability
If high voltage transistors are used for memory operations, then programming and erasing capabilities are improved, but compatibility with logic process voltage limits deteriorates
Solution Approach 1:
The patent segments the gate control function into two independent gates: the first gate is optimized for logic operations at standard voltages, while the second gate is dedicated to memory programming and erasing operations at higher voltages. This segmentation allows each gate to operate at its optimal voltage level without compromising the other, achieving both high voltage memory capabilities and logic process compatibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes additional processing steps and costs while enabling efficient integration of non-volatile memory with logic circuits, offering faster erase times and lower operating voltages, and maintains compatibility with existing logic processes.
Implementation Method 1
using techniques like Fowler-Nordheim tunneling and Band-to-band hot-hole injection for programming and erasing
Implementation Method 2
using techniques like Fowler-Nordheim tunneling and Band-to-band hot-hole injection for programming and erasing
Data Source
AI summary
A system and method of an electrically programmable and erasable non-volatile memory cell fabricated using a single-poly, logic process with the addition of ONO deposition and etching is disclosed. In one embodiment, a non-volatile memory system includes at least one non-volatile memory cell consists of a SONOS transistor fabricated on a P substrate, with a deep N-well located in the P substrate, with a P-well located in the deep N-well. The memory cell further includes an access NMOS transistor, coupled to the SONOS transistor and located in the same P-well that includes an oxide only gate-dielectric. The cell can be fabricated in a modified logic process with other transistors and with their physical characteristics preserved.