Antifuse OTP Memory Bit Cell Without Access Transistor
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Solution Overview
Problem
Current antifuse one-time programmable (OTP) memory bit cells in CMOS integrated circuits face challenges in achieving small bit cell size, tight read current distribution, low power consumption, and high reliability while maintaining compatibility with CMOS processes and scalability, especially as feature dimensions shrink and voltage requirements vary between interior and I/O circuits.
Innovation Solution
The proposed antifuse OTP memory bit cell design features a MOS capacitor with a gate electrode, thin dielectric, and diffusion regions in a semiconductor substrate, where adjacent source/drain diffusion regions can be connected under the gate, forming a diode or JFET in conjunction with a diode upon programming, eliminating the need for an access MOSFET and allowing for self-addressability without additional manufacturing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a 1T1C antifuse OTP memory bit cell is used, then data security and reliability are improved, but bit cell size and power consumption increase
Solution Approach 1:
The patent extracts and removes the access MOSFET from the traditional 1T1C antifuse OTP memory bit cell structure, retaining only the MOS capacitor (antifuse) element. This extraction reduces the bit cell area while maintaining the core antifuse functionality for data storage and security applications.
Solution Approach 2:
The patent implements self-addressable antifuse bit cells that can be selectively programmed and read without requiring external access transistors. The antifuse structure itself provides the addressing capability through its electrical characteristics, eliminating the need for additional access devices and reducing overall bit cell size.
2Reliability
If a 1T1C antifuse OTP memory bit cell is used, then data security and reliability are improved, but power consumption increases
Solution Approach 1:
The patent removes the access MOSFET from the bit cell structure, eliminating the parasitic leakage currents and dynamic power consumption associated with the access transistor. This extraction significantly reduces the overall power consumption of the memory device while maintaining antifuse reliability.
Solution Approach 2:
The self-addressable antifuse bit cells operate with minimal power consumption by utilizing the inherent electrical characteristics of the antifuse structure for both addressing and data storage functions, eliminating the need for additional power-hungry access transistors.
3Ease of manufacture
If traditional antifuse OTP memory design is used, then manufacturing compatibility is maintained, but device complexity and scalability are limited
Solution Approach 1:
The patent extracts the access MOSFET from the traditional 1T1C design, simplifying the bit cell structure to contain only the MOS capacitor (antifuse) element. This simplification reduces device complexity while maintaining compatibility with standard CMOS manufacturing processes for the antifuse structure itself.
Solution Approach 2:
The simplified antifuse bit cell structure serves multiple functions: it acts as both the storage element and the addressable unit, eliminating the need for separate access transistors. This multi-functionality reduces device complexity while maintaining manufacturing compatibility through standard CMOS antifuse fabrication processes.
4Productivity
If feature dimensions are shrunk for scaling, then productivity and integration density are improved, but read current distribution uniformity and reliability deteriorate
Solution Approach 1:
The self-addressable antifuse bit cells maintain uniform read current distribution through their inherent electrical characteristics, which are less sensitive to dimensional variations compared to designs requiring access transistors. This self-service capability enables reliable operation at scaled dimensions with improved integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves a compact bit cell with uniform read current distribution, low power consumption, and high reliability, compatible with CMOS processes, and facilitates easy scaling into nanometer nodes without increasing manufacturing costs, thereby meeting performance and cost requirements for wide-ranging OTP memory applications.
Implementation Method 1
In a fresh antifuse, i.e., in an antifuse in unprogrammed state, the dielectric layer blocks current flow between the two conducting material, or electrodes.
Implementation Method 2
Programming of an antifuse is accomplished by applying a voltage between the two electrodes that is high enough to cause the dielectric to break down. After dielectric breakdown, antifuse can conduct current, i.e., the antifuse is in programmed state.
Data Source
AI summary
An antifuse OTP memory bit cell comprises a gate electrode, a gate dielectric and source/drain diffusions formed in an active area of a semiconductor substrate. The source/drain diffusions are connected under the gate electrode by lateral diffusion but they don't have to be. If connected, a rectifying contact is created in a programmed bit cell. If unconnected, a rectifying contact or a non-rectifying contact is created in a programmed bit cell. Whether connected or unconnected, the device operates as an OTP memory bit cell without an access transistor.