Stacked Semiconductor Device for AI Processing Speed and Power Reduction
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Solution Overview
Problem
In AI technology, the repeated product-sum operations using weight data and input data lead to increased power consumption and heat generation due to high arithmetic operation frequencies, which is exacerbated by the need for large memory cell arrays and dedicated arithmetic circuits, resulting in inefficient semiconductor devices.
Innovation Solution
A semiconductor device with a stacked structure comprising multiple memory circuits, a switching circuit, and arithmetic circuits, where the memory circuits retain weight data and intermediate data, and the switching circuit facilitates efficient data transfer between these components, reducing power consumption and increasing processing speed by minimizing bit line length and parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If arithmetic operation frequency is increased to improve AI processing speed, then productivity is improved, but power consumption and heat generation increase
Solution Approach 1:
The patent transitions from planar arrangement to three-dimensional stacked architecture, placing memory circuits and arithmetic circuits in different layers connected via vertical bit lines. This dimensional change enables simultaneous access to multiple memory cells through parallel bit lines, increasing arithmetic processing speed while distributing power consumption across multiple layers and reducing heat concentration in any single region.
Solution Approach 2:
The patent divides the computational system into multiple independent memory circuits and arithmetic circuits that can operate in parallel. Each memory circuit-bit line pair functions as an independent computational unit, allowing simultaneous product-sum operations on different data sets. This segmentation increases overall processing throughput while distributing power consumption across multiple smaller units rather than concentrating it in a single high-frequency processor.
2Quantity of substance
If memory cell array size is increased to retain more weight data, then storage capacity is improved, but circuit area increases
Solution Approach 1:
The patent utilizes vertical stacking to extend memory capacity into the third dimension. Multiple memory circuits are arranged in different layers along the vertical axis, connected to arithmetic circuits through bit lines. This stacked configuration provides large storage capacity while maintaining a compact footprint area, as the memory expands upward rather than outward horizontally.
3Loss of energy
If bit line length is shortened to reduce charge and discharge energy, then power consumption is reduced, but circuit layout complexity increases
Solution Approach 1:
The patent introduces vertical bit lines that extend through multiple layers to connect memory circuits in different stacked positions to arithmetic circuits. This vertical routing approach allows bit lines to serve multiple memory cells across layers, effectively reducing the horizontal length of bit lines and minimizing charge/discharge energy requirements, while the modular stacked architecture manages layout complexity through systematic layering.
4Productivity
If dedicated arithmetic circuits are added to perform AI operations, then arithmetic processing capability is improved, but device complexity increases
Solution Approach 1:
The patent merges memory and arithmetic functions into a unified stacked architecture where memory circuits and arithmetic circuits are tightly integrated across multiple layers. The bit lines serve dual purposes as both memory readout lines and arithmetic operation inputs. This merging reduces the need for separate dedicated AI processing units while maintaining enhanced arithmetic capability, thereby limiting the increase in overall device complexity.
Data Source
AI summary
A semiconductor device with a novel structure is provided. The semiconductor device includes a plurality of memory circuits, a switching circuit, a first arithmetic circuit, and a second arithmetic circuit. The plurality of memory circuits each have a function of retaining weight data. The switching circuit has a function of switching electrical continuity and discontinuity between any one of the memory circuits and the first arithmetic circuit. The first arithmetic circuit outputs a first output signal based on product-sum operation processing of input data and the weight data selected by the switching circuit to the second arithmetic circuit. A layer including the plurality of memory circuits is provided to be stacked over a layer including the switching circuit, the first arithmetic circuit, and the second arithmetic circuit.