NAND Memory Gate Structure Sidewall Uniformity
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Solution Overview
Problem
In NAND memory manufacturing, the Iso/Dense loading effect and interlayer alignment deviations during photolithography lead to uneven critical dimensions of control gates and spacing issues between control and select gates, reducing the process window and utilization ratio of memory products.
Innovation Solution
A method involving sequential photolithography and etching processes with specific mask and photoresist layers to form uniform sidewall structures, ensuring consistent critical dimensions and reducing the need for dummy gates, thereby addressing the Iso/Dense loading effect and alignment deviations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If self-aligned double patterning technology is used to reduce critical dimension, then storage unit density is improved, but Iso/Dense loading effect causes uneven critical dimensions of control gates
Solution Approach 1:
The patent applies preliminary action by forming dummy gates in advance before the main patterning process. These dummy gates are strategically placed to provide additional loading during etching, which compensates for the Iso/Dense loading effect and ensures uniform critical dimensions across all control gates, including those on the outer side that would otherwise be affected by uneven etching rates.
Solution Approach 2:
The patent applies local quality by differentiating between key patterns and non-key patterns in the photomask design. The dummy gates are selectively placed only in specific locations where loading compensation is needed, rather than uniformly across the entire structure. This localized approach addresses the uneven critical dimension problem in affected areas while maintaining high density in other regions.
2Ease of manufacture
If photolithography is performed to pattern gates, then gate structures are formed, but interlayer alignment deviation causes uneven spacing between control gate and select gate
Solution Approach 1:
The patent applies merging by combining the control gate pattern and select gate pattern into a single photomask layer. This simultaneous patterning approach ensures that both gates are formed in the same photolithography exposure step, eliminating interlayer alignment deviations that would occur with separate patterning steps and ensuring uniform spacing between control gates and select gates.
Solution Approach 2:
The patent uses a combined photomask pattern as an intermediary that defines both control gate and select gate positions in a single exposure. This unified pattern template ensures precise relative positioning and uniform spacing between different gate types, overcoming the alignment accuracy limitations of multi-step photolithography processes.
3Productivity
If control gate critical dimension is reduced to increase storage capacity, then storage density is improved, but process window is reduced
Solution Approach 1:
The patent applies parameter changes by modifying the etching process parameters through the introduction of dummy gates. The additional loading from dummy gates changes the etching rate and plasma chemistry parameters, enabling better control over the critical dimension of control gates at reduced sizes. This allows high storage density to be achieved while maintaining an adequate process window through optimized etching conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the uniformity of device performance, increases the utilization ratio of memory area, and broadens the process window by ensuring consistent sidewall widths and reducing the reliance on dummy gates.
Implementation Method 1
performing a first-pass photolithography process by using a first photomask and a first photoresist layer
Implementation Method 2
performing an etching process to the organic dielectric Tri-Layer and the TEOS structure, removing the organic dielectric Tri-Layer to form a control gate structure
Data Source
AI summary
A method for forming the gate structure of the NAND memory, comprising the steps of disposing a gate structure layer, a pattern transfer layer, a TEOS structure, and an organic dielectric Tri-Layer on a substrate sequentially; performing a patterning using a first photomask and a first photoresist layer; performing an etching process to form a control gate structure, a peripheral gate structure and a select gate structure; performing a trimming process to them; patterning sidewalls on sides of them; performing a second patterning using a second photomask as a mask and a second photoresist layer to protect the peripheral gate structure, the select gate structure, and their sidewalls; removing the control gate structure between its sidewalls; performing etching by using the sidewalls, the peripheral gate structure and the select gate structure as masks to form the control gate, the peripheral gate, and the select gate.