ESD Protection Circuit with Dynamic Snapback Voltage Control
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Solution Overview
Problem
Existing ESD protection circuits with low snapback voltage are susceptible to improper activation by non-ESD voltage spikes and ripples, which can lead to unintended operation and potential damage.
Innovation Solution
A three-terminal snapback device, such as a MOS-based LDMOS SCR, is used in conjunction with a control circuit that dynamically adjusts the snapback voltage in response to voltage changes, incorporating a turn-on and turn-off circuit to manage snapback voltage levels, ensuring the circuit remains immune to non-ESD events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the snapback voltage is lowered to improve ESD protection effectiveness, then the protection capability against ESD events is enhanced, but the circuit becomes susceptible to improper activation by non-ESD voltage spikes and ripples
Solution Approach 1:
The patent implements dynamic snapback voltage adjustment by introducing a control terminal that receives a control signal to modulate the snapback voltage level. During normal operation, the snapback voltage is maintained at a higher level to prevent false triggering by voltage spikes. During ESD events, the snapback voltage is dynamically lowered to enhance protection effectiveness, thereby resolving the contradiction between protection capability and susceptibility to non-ESD disturbances.
Solution Approach 2:
The patent changes the snapback voltage parameter from a fixed value to a variable value that can be adjusted based on operating conditions. By introducing a control signal that modifies the snapback voltage parameter, the system achieves high snapback voltage during normal operation to avoid false triggering, and low snapback voltage during ESD events to provide effective protection, thus resolving the technical contradiction.
2Object-affected harmful factors
If a control circuit is added to dynamically adjust snapback voltage, then immunity to non-ESD events is improved, but the device complexity increases
Solution Approach 1:
The control terminal is integrated into the existing snapback device structure, allowing the same device to perform both ESD protection and normal signal processing functions. The control terminal receives control signals that enable the snapback device to adapt its characteristics based on operating mode, achieving multi-functionality without requiring separate dedicated circuits for ESD protection and normal operation, thus minimizing complexity increase.
Solution Approach 2:
The control circuit is designed to automatically detect voltage spike conditions and adjust the snapback voltage accordingly without requiring external intervention or complex control logic. The system uses inherent voltage detection mechanisms to trigger appropriate snapback voltage levels, enabling the circuit to self-regulate and protect itself from non-ESD events while maintaining simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively lowers the snapback voltage only during ESD events while maintaining a higher voltage threshold during normal conditions, thereby preventing improper activation by non-ESD voltage spikes and ripples, enhancing the protection circuit's reliability and effectiveness.
Implementation Method 1
when the voltage across nodes 134 and 144 is positive and equal to or greater than the snapback voltage, the reverse-biased junction breaks down due to avalanche multiplication. The breakdown of the junction causes a large number of holes to be injected into p− well 122, and a large number of electrons to be injected into n− well 120.
Implementation Method 2
LDMOS SCR 200 operates the same as SCR 100 except that gate 214 substantially lowers the snapback voltage. When the NMOS transistor operation of LDMOS SCR 200 turns on, electrons flow from n+ region 140 to n+ region 130. The rising voltage on n− well 120 along with the flow of electrons into n− well 120 causes the pn junction between n− well 120 and p− well 122 to break down at a much lower snapback voltage than the snapback voltage of SCR 100.
Data Source
AI summary
A three-terminal snapback device is utilized with a control circuit to provide a low snapback voltage that is protected from non-ESD voltage spikes and ripples. In response to a fast edge, the control circuit lowers the snapback voltage, unless a status signal indicates that normal operating voltages are present, and raises the snapback voltage a predefined time later. If the fast edge represents an ESD pulse, SCR operation is initiated at the lowered snapback voltage. If the fast edge represents a power on sequence, the maximum voltage is less than the momentarily lowered snapback voltage and therefore insufficient to initiate SCR operation. Further, once normal operating voltages are present, the control circuit continuously maintains the raised snapback voltage so that a non-ESD voltage spike or ripple can not improperly turn on the snapback device.