3D Logic-Memory Structure With Monocrystalline Channels and Shorter Wiring
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Solution Overview
Problem
Wires in integrated circuits (ICs) dominate performance, functionality, and power consumption as they degrade with scaling, while existing 3D memory technologies often use polysilicon for active memory cell channels, leading to higher cell-to-cell performance variations and lower drive than monocrystalline channels.
Innovation Solution
The development of 3D IC devices with monocrystalline channels constructed using alternative methods to ion cut and successive layer transfers, incorporating oxide-to-oxide bonds and various metal layers with transistors, and including features like voltage regulators, power down control circuits, and antifuse structures, to enhance performance and reduce construction costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If polysilicon is used for active memory cell channels in 3D memory, then construction costs are reduced and manufacturing is simplified, but cell-to-cell performance variations increase and drive current decreases
Solution Approach 1:
The patent changes the material parameter from polysilicon to monocrystalline silicon for the channel region. This parameter change fundamentally alters the electrical properties, reducing carrier mobility variations and improving drive current while maintaining manufacturing feasibility through selective epitaxial growth processes
Solution Approach 2:
The patent employs a composite structure where monocrystalline silicon is used specifically for the channel region while other parts of the device may use different materials. This selective material composition optimizes performance in the critical channel region without requiring the entire device to be constructed with high-cost monocrystalline material
2Reliability
If monocrystalline channels are used in 3D memory, then cell-to-cell performance variations are reduced and drive current is enhanced, but construction costs and manufacturing complexity increase
Solution Approach 1:
The patent segments the device structure into different regions with different material requirements. The channel region is specifically formed with monocrystalline silicon through selective epitaxial growth, while other regions may use simpler materials. This segmentation allows performance optimization in the critical channel region without applying the complex and costly monocrystalline fabrication process to the entire device
Solution Approach 2:
The patent transitions from planar 2D memory architecture to three-dimensional stacked architecture with vertical channels. This dimensional change allows monocrystalline channels to be formed through vertical epitaxial growth, improving performance while the stacking approach increases density without proportionally increasing manufacturing complexity
3Productivity
If wires are scaled down to improve transistor density, then transistor performance and density improve, but wire performance degrades and power consumption increases
Solution Approach 1:
The patent transitions from two-dimensional planar interconnects to three-dimensional vertical interconnects through TSV technology. This dimensional change allows signals to travel vertically through the substrate rather than laterally across the surface, significantly reducing wire length and associated power consumption while enabling higher transistor density through stacked device architecture
Solution Approach 2:
The patent implements nested interconnect structures where multiple wiring layers are stacked vertically with TSVs providing through-substrate connections. This nested arrangement allows compact integration of multiple interconnect levels, reducing the overall footprint and enabling continued scaling of transistor density without proportional increases in wire length and power consumption
Data Source
AI summary
A 3D semiconductor device including: a first level including a single crystal layer, a memory control circuit, a first metal layer, a second metal layer, and a third metal layer; connection of the first transistors comprises the first, and/or the second, and/or the third metal layer; a fourth metal layer disposed atop third transistors disposed atop second transistors disposed atop said first level; a memory array including word-lines and at least four memory mini arrays which include at least four rows by four columns of memory cells, each of the memory cells includes at least one of the second transistors (at least one with a metal gate) or at least one of the third transistors; a connection path from the fourth metal to the third metal including a via disposed through the memory array; the memory control circuit includes first transistors and voltage regulators.