3D Memory Multiplexor Layout for Higher Cell Density
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Solution Overview
Problem
As design rules shrink, semiconductor space for fabricating DRAM arrays decreases, leading to challenges in increasing memory cell storage density due to limited space for circuitry under the array.
Innovation Solution
The implementation of a vertical three-dimensional (3D) memory architecture with multiplexors that allow vertical sense lines to be activated and deactivated, simplifying circuitry by relocating sense amplifiers outside the array, thereby optimizing space for more memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If circuitry is placed under the DRAM array to save space, then manufacturing density improves, but device complexity increases due to the need for sense amplifiers and multiplexors in the limited space
Solution Approach 1:
The patent extracts sense amplifiers from the space under the DRAM array and relocates them to peripheral areas. This removal reduces the complexity of circuitry that must be integrated in the limited space beneath the memory cells, while still providing all necessary sensing and amplification functions through the multiplexor system that remains under the array.
2Reliability
If more circuitry is integrated under the array to maintain access functionality, then reliability improves, but available space for memory cells decreases
Solution Approach 1:
The multiplexors under the array are designed to perform multiple functions: they serve as access device control elements, act as signal routing switches, and provide connection points for both read and write operations. This multi-functionality reduces the need for separate dedicated circuitry for each function, thereby preserving space for memory cells while maintaining complete access functionality.
3Quantity of substance
If vertical stacking is implemented to increase density, then storage capacity improves, but heat dissipation becomes more difficult due to stacked architecture
Solution Approach 1:
The patent transitions from a planar two-dimensional memory layout to a three-dimensional vertically stacked architecture. By stacking multiple tiers of memory cells vertically, the design achieves higher storage density within the same footprint while distributing heat generation across multiple vertical layers, improving thermal management compared to dense planar arrangements.
Data Source
AI summary
A sense amplifier can be formed outside of/horizontally adjacent to an array of vertically stacked tiers of memory cells. Memory cells can be sensed via multiplexors formed under the array that can operate to couple vertical sense lines (to which the memory cells are coupled) to horizontal sense lines (to which the sense amplifier is coupled).