3D Memory Multiplexor Layout for Higher Cell Density
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Solution Overview
Problem
As design rules shrink, semiconductor space for fabricating DRAM arrays decreases, leading to challenges in increasing memory cell storage density due to the need for sense amplifiers within the array, which occupy valuable space.
Innovation Solution
The implementation of a vertical 3D memory architecture with multiplexors that allow vertical sense lines to be activated and deactivated, eliminating the need for sense amplifiers within the array and enabling more efficient use of space by locating them outside or adjacent to the array, thereby increasing cell storage density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sense amplifiers are placed within the DRAM array to enable memory operations, then memory functionality is achieved, but semiconductor space for fabricating memory cells is reduced
Solution Approach 1:
The patent transitions from a 2D planar memory architecture to a 3D vertical architecture by stacking multiple memory cell tiers vertically. This dimensional change allows sense amplifiers to be positioned in the vertical dimension (below the array) rather than competing for horizontal plane space, thereby maintaining memory functionality while preserving semiconductor fabrication space.
Solution Approach 2:
The patent extracts sense amplifiers from the memory cell array and relocates them to positions outside the array (below the memory tiers). This separation removes the space conflict between sense amplifiers and memory cells, allowing the array to be densely packed with memory cells while sense amplifiers occupy separate real estate.
2Quantity of substance
If more memory cells are packed into the same semiconductor space to increase storage density, then storage capacity increases, but space for access circuitry becomes insufficient
Solution Approach 1:
By organizing memory cells into vertically stacked tiers and using vertical sense lines that extend through multiple tiers, the patent exploits the vertical dimension to increase storage density without proportionally increasing the footprint for access circuitry. The sense amplifiers serve multiple vertical tiers simultaneously.
Solution Approach 2:
The sense amplifiers positioned below the array serve multiple memory cell tiers through vertical sense lines, making them multi-functional. A single sense amplifier can access and read/write data from multiple tiers, reducing the total number of sense amplifiers needed and freeing up semiconductor space.
3Productivity
If vertical sense lines are used to access multiple memory tiers, then access efficiency improves, but control complexity increases requiring multiplexors
Solution Approach 1:
The patent introduces multiplexors as intermediary devices between the word lines and vertical sense lines. These multiplexors act as smart switches that selectively connect specific word lines to specific vertical sense lines based on the desired memory cell address, enabling efficient access to specific tiers while managing the complexity of vertical sensing.
Solution Approach 2:
The multiplexors provide dynamic, selective connectivity between word lines and vertical sense lines. Rather than fixed connections, the multiplexors can reconfigure which memory tiers are accessed based on control signals, enabling flexible and efficient access to different portions of the stacked memory array.
Data Source
AI summary
A sense amplifier can be formed outside of/horizontally adjacent to an array of vertically stacked tiers of memory cells. Memory cells can be sensed via multiplexors formed under the array that can operate to couple vertical sense lines (to which the memory cells are coupled) to horizontal sense lines (to which the sense amplifier is coupled).