Read-Only Memories TRIZ Cases

Independent bulk-voltage and buffer control let a shared 1T eFuse power circuit save area while reducing leakage and protecting read accuracy.

Multilevel analog storage with memristors shrinks CAM area and power while enabling differentiable search without analog-digital conversion.

An external-voltage delay correction circuit trims write strobe timing in memory while avoiding the power cost of internal high-voltage generation.

Controls Flash memory bit-line discharge with current mirrors and staggered enable signals to prevent peak current spikes and shorten discharge time.

A read-trained data strobe is reused for write duty correction, reducing memory training time and power without separate signals.

A two-stage PMOS high-voltage transfer path applies OTP program voltage stepwise to prevent gate oxide breakdown, bulk current, and read failure.

A DAC and bistable multivibrator preserve 1-bit relay state through power loss, avoiding complex microcontroller or magnetic designs.

Per-die fitting equations replace large lookup tables to track temperature-driven voltage shifts across program-erase cycles and lower raw bit errors.

Grounding the target column and isolating programming pulses cuts static and dynamic sneak currents in larger crossbar arrays.

Electric-field threshold programming replaces SRAM in FPGA LUT cells to cut leakage and area while preserving non-volatile data storage.

Cross-coupled latches and synchronized write signals help SRAM cells recover from radiation-induced state changes and prevent data corruption.

Gated memory cells combine storage and logic on a shared bit line to cut data-movement time and power during parallel processing.

Mixed-polarity pull-up and pull-down switching linearizes output current and voltage to cut noise and distortion in multi-level signaling.

Stacked PMOS and NMOS memory circuits split programming voltage across core devices to prevent breakdown, cut area, and keep high-speed operation.

Concurrent programming with event detection disconnects two-terminal memory cells early to prevent invalid identifier bits and cut power use.

Dual cross-coupled latches with synchronized write signals keep identical memory states and recover stored data after radiation upsets.

Monotonic ECC-coded pointers let OTP banks act as reprogrammable memory blocks while preserving valid updates and readable data.

Embedding controller circuitry into MRAM cuts PCB space and interconnects while enabling faster direct communication with FPGA.

Reference-voltage sensing switches memory devices between parallel and source-synchronous clocking to reduce skew, noise, and power.

Output-to-gate diode feedback keeps a memory high-voltage switch out of the Fowler-Nordheim regime, extending transistor lifetime.

Multiplexors under stacked memory tiers route vertical sense lines to external sense amplifiers, freeing array area for higher cell density.

An interface circuit auto-switches between 3.3 V and 1.8 V host signals, removing jumpers and separate boards for PCIe memory integration.

Passive low-pass filtering derives a representative bus duty cycle, enabling trim calibration across parallel paths to cut high-speed signal errors.

Charge accumulation and matched current scaling let this common counter ADC cut power use while keeping neural compute stable across temperature changes.

A multiplexed AMPI read architecture lets NAND Flash accept multi-plane read commands during busy states, improving read speed and flexibility.

Calibration circuits tune neural network synapse weights to offset memory-cell variability and temperature drift while preserving accuracy.

Timed pre-charge and clocked NAND gating reduce unnecessary transistor switching, lowering memory circuit power use.

Current-demand feedback adjusts deboost voltage during memory reads to offset threshold shifts and improve multi-level cell sensing accuracy.

A 2.0V detector disables lower-threshold detectors above the trigger point, cutting NAND flash power use without losing voltage monitoring accuracy.

Independent bulk-voltage control lets a shared PMOS pass transistor save area while limiting read leakage in eFuse circuits.

Stacked PMOS and NMOS selectors with level shifting let memory arrays handle programming voltage above core-device breakdown without larger I/O devices.

Nonvolatile threshold tuning in charge trap transistors compensates CMOS process variation to improve yield, SRAM read speed, and energy use.

A stacked NMOS and pre-charged gate capacitance delay sense triggering so low-voltage SRAM reads gain enough bitline differential.

Switching global, string select, and word line voltages across sensing phases cuts setup time and eases the IO bottleneck in in-memory MAC.

Moving-average clock calibration aligns TI-ADC sampling intervals to cut timing skew, suppress spurs, and improve high-speed signal quality.

Prestored trimming shift values let stacked memory chips adjust setup-hold timing by chip count, avoiding fuse limits and added programming area.

A capacitive pull-down circuit drives the SRAM ground node below ground during read and write operations to improve stability and write efficiency.

Compressed LLR updates from multiple hard reads cut memory use and latency while improving non-volatile memory decoding reliability.

A NAND flash decoder uses decoding success trends to reorder read voltages, cutting retry time while preserving error recovery.

Time-encoded analog pulses route neural signals through FPGA interconnects without op-amp buffers, cutting die area, power, and conversion errors.

Grounding the target column and pre-charging unselected rows suppress static and dynamic sneak currents during crossbar array programming.

A shared control memory feeds plane-specific micro-control circuits in sequence, cutting multi-plane memory size and control complexity.

Power-gated memory with cross-domain level shifting prevents wordline glitches, false writes, and retention loss during power-up.

Using NAND flash synapse strings instead of memristors improves binary neural network reliability, integration, and power efficiency.

A configurable logic circuit loaded from non-volatile memory enables fast error correction, self-test, and flexible flash control after power-on.

Parallel gated memory cells drive a shared bit line to compute data in memory, cutting data-movement time, power use, and equalization overhead.

Representative duty-cycle sensing and trim adjustment correct local distortion across parallel data bus paths, improving high-speed signal accuracy.

Automatic voltage switching and level shifting let a memory interface handle 1.8 V and 3.3 V operation without separate boards or jumpers.

Boost timing is tuned to each stacked NAND chip's distortion profile, improving eye aperture and controller-to-memory signal quality.

Shared level conversion and staged decoding cut word line decoder area and memory cost in high-capacity FLASH chips.