VT-Programmable FET Memory Cells for Non-Volatile FPGA LUTs

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Field programmable gate arrays (FPGAs) face challenges with look-up tables (LUTs) implemented using static random access memory (SRAM) cells, which are volatile, large, and consume significant power due to excessive leakage current, making them unsuitable for modern integrated circuit design requirements of size scaling, power scaling, and performance.

Innovation Solution

The development of a threshold voltage (VT)-programmable field effect transistor (FET)-based memory cell, which includes a first transistor and a second transistor with electric field-based programmable threshold voltage, connected in series between voltage source lines, and a sense node at their junction, allowing for non-volatile data storage with reduced leakage and footprint.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If static random access memory (SRAM) cells are used to implement look-up tables (LUTs) in field programmable gate arrays (FPGAs), then the LUTs can store data, but the memory cells are volatile, large, and consume significant power due to excessive leakage current

Engineering Contradiction:

Improvedata storage capabilityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The patent changes the fundamental parameter of memory cell type from volatile SRAM to non-volatile floating gate FET, which fundamentally alters the power consumption characteristics by eliminating the need for continuous refresh operations and reducing leakage current while maintaining data storage capability

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent replaces the mechanical/electrical refresh mechanism required by volatile SRAM with a charge trapping mechanism in floating gate FETs, where data is stored as trapped charge that persists without power, thereby eliminating the continuous power consumption associated with maintaining volatile memory state

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Reliability

Engineering Contradiction:

Improvedata storage capabilityVSAvoidmemory cell area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent changes the memory cell type from SRAM to floating gate FET, which has a fundamentally different structure that occupies less area while providing non-volatile storage, thereby reducing the area footprint of LUTs in FPGAs

Inventive Principle:

Principle #35Parameter changes

3Reliability

Engineering Contradiction:

Improvedata retentionVSAvoidleakage current

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent changes from volatile SRAM to non-volatile floating gate FET, which inherently has lower leakage current because the stored charge is trapped in the floating gate and does not leak, thereby eliminating the harmful leakage current while maintaining data retention

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent replaces the volatile memory mechanism that requires continuous refreshing with a charge trapping mechanism where data is stored in the floating gate, eliminating the need for refresh operations and the associated leakage current

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution enables the creation of a more efficient LUT that consumes less area and power, using multiplexing circuits with multiple VT-programmable FET-based memory cells, allowing for effective data storage and retrieval with improved performance and reduced spurious outputs.

Implementation Method 1

a second transistor with electric field-based programmable threshold voltage

Methodology Applied

Scientific EffectElectric field-based programmable threshold voltage: Electric Field

Data Source

PatentUS12190930B2Threshold voltage-programmable field effect transistor-based memory cells and look-up table implemented using the memory cells

Publication Date: 2025.01.07 GLOBALFOUNDRIES US INC

AI summary

Disclosed is threshold voltage (VT)-programmable field effect transistor (FET)-based memory cell including a first transistor and a second transistor (which has an electric-field based programmable VT) connected in series between two voltage source lines. The gates of the transistors are connected to different wordlines and a sense node is at the junction between the two transistors. In preferred embodiments, the first transistor is a PFET and the second transistor is an NFET. Different operating modes (e.g., write 0 or 1 and read) are achieved using specific combinations of voltage pulses on the wordlines and voltage source lines. The memory cell is non-volatile, exhibits relatively low leakage, and has a relatively small footprint as compared to a conventional memory cell. Also disclosed are a look-up table (LUT) incorporating multiple threshold voltage (VT)-programmable field effect transistor (FET)-based memory cells and associated methods.