NAND-Based Memory Circuit Pre-Charge to Cut Toggle Power
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) become smaller and more complex, the resistance of conductive lines affects operating voltages and overall IC performance, leading to increased power consumption due to unnecessary toggling transistors in memory circuits.
Innovation Solution
Incorporating a NAND logic gate with specific configurations of N-type and P-type transistors, including a first N-type transistor between the second N-type transistor and the voltage supply node of the NAND logic gate, which can be disabled by a pre-charge signal, reducing the number of toggling transistors and thus power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional memory circuit configurations are used, then the circuit can operate with standard transistor arrangements, but power consumption increases due to unnecessary toggling transistors
Solution Approach 1:
The patent extracts and removes unnecessary toggling transistors from the conventional memory circuit configuration. By identifying and eliminating transistors that cause unnecessary switching activity, the circuit achieves reduced power consumption while maintaining its essential functionality through a simplified transistor arrangement.
Solution Approach 2:
The patent implements dynamic control of transistor switching through carefully timed pre-charge signals and clock signals. The first N-type transistor is enabled only during specific operation phases (write or read), preventing unnecessary toggling during other phases. This dynamic switching strategy reduces power consumption by ensuring transistors are active only when needed.
2Loss of energy
If the number of transistors is reduced to minimize toggling, then power consumption decreases, but the circuit may lose functionality or reliability
Solution Approach 1:
The patent applies preliminary action by pre-charging specific nodes (such as the first voltage supply node of the NAND logic gate) before actual memory operations. The pre-charge signal ensures that nodes are properly initialized to known states, maintaining circuit reliability even with reduced transistor counts. This preliminary preparation prevents unintended behavior during subsequent read or write operations.
Solution Approach 2:
The patent introduces intermediary control signals (pre-charge signal and clock signal) that mediate between the reduced transistor configuration and the required circuit functionality. These intermediary signals coordinate the switching behavior of the remaining transistors, ensuring that the simplified circuit structure still performs reliable memory operations without unnecessary toggling.
Data Source
AI summary
A memory circuit includes a NAND logic gate configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The memory circuit further includes a first N-type transistor coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The memory circuit further includes a second N-type transistor coupled to the first N-type transistor and a reference voltage supply, and configured to receive a first clock signal. The memory circuit further includes a first latch coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.