NAND Flash Multi-Plane Read Control for Busy-State Asynchrony
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Solution Overview
Problem
Existing NAND Flash memory devices perform multi-plane read operations synchronously, limiting system performance as the host cannot issue read instructions when the memory device is busy, restricting operation speed and efficiency.
Innovation Solution
Implementing an asynchronous multi-plane independent read operation architecture with a main microcontroller unit (MCU) and multiple asynchronous multi-plane independent (AMPI) read units, along with a multiplexing circuit to manage control signals, allowing for independent read operations across memory planes even when the device is busy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If synchronous multi-plane read operation is used, then control simplicity is maintained, but system performance and read speed are limited because the host cannot issue read instructions when the memory device is busy
Solution Approach 1:
The control architecture is segmented into a main MCU and multiple independent AMPI read units (first AMPI read unit, second AMPI read unit, etc.). Each AMPI read unit is responsible for controlling read operations on specific memory planes independently. This segmentation allows parallel processing of read operations across multiple planes simultaneously, enabling the host to issue multiple read instructions without waiting for previous operations to complete, thereby resolving the contradiction between maintaining control simplicity and improving system performance.
Solution Approach 2:
The multiplexing circuit acts as an intermediary between the control units (main MCU and AMPI read units) and the memory planes. It intelligently routes control signals from the appropriate source to the target memory plane based on the operation type. For AMPI read operations, it directs control signals from the corresponding AMPI read unit; for non-AMPI read operations, it directs control signals from the main MCU. This intermediary mechanism enables complex parallel operations while maintaining a relatively simple interface with the host, resolving the contradiction between operational capability and control simplicity.
2Speed
If asynchronous multi-plane independent read operation is implemented, then read speed and operational flexibility are improved, but control signal management complexity increases
Solution Approach 1:
The control functionality is divided and distributed across multiple independent AMPI read units, with each unit dedicated to specific memory planes. This segmentation enables simultaneous independent control of multiple memory planes, allowing the system to execute multiple read operations in parallel at different speeds and timing, thereby achieving high read speed without requiring complex centralized control signal management.
Solution Approach 2:
Each AMPI read unit is designed with multi-functionality to handle various read operations on its assigned memory planes. These units can independently generate and manage control signals for different read operations, reducing the need for complex signal routing and management logic. The multiplexing circuit further enhances this by universally handling signal distribution from multiple sources to multiple destinations based on operation type, simplifying overall control signal management while enabling asynchronous operations.
3Adaptability or versatility
If multiple AMPI read units are introduced, then independent read operations on multiple planes are enabled, but device structure becomes more complex
Solution Approach 1:
The device structure is segmented into modular components: a main MCU and multiple independent AMPI read units, each responsible for specific memory planes. This modular segmentation provides operational flexibility as each unit can independently execute read operations on its assigned planes without interfering with other units. The segmented architecture allows the system to adapt to different operational scenarios by activating only the necessary units, maintaining versatility while managing structural complexity through clear functional separation.
Solution Approach 2:
The multiplexing circuit merges the control signal paths from the main MCU and multiple AMPI read units into a unified interface for the memory planes. This merging mechanism allows the system to present a simplified external interface while internally supporting multiple independent operation modes. By combining control functions and signal paths through the multiplexing circuit, the device achieves high operational flexibility without proportionally increasing external interface complexity.
Data Source
AI summary
In certain aspects, a method for operating a memory device is disclosed. The memory device includes memory planes and multiplexers (MUXs). Each MUX includes an output coupled to a respective one of the memory planes, a first input receiving a non-asynchronous multi-plane independent (AMPI) read control signal, and a second input receiving an AMPI read control signal. Whether an instruction is an AMPI read instruction or a non-AMPI read instruction is determined. In response to the instruction being an AMPI read instruction, an AMPI read control signal is generated based on the AMPI read instruction, and a corresponding MUX is controlled to enable outputting the AMPI read control signal from the second input to the corresponding memory plane. In response to the instruction being a non-AMPI read instruction, a non-AMPI read control signal is generated based on the non-AMPI read instruction, and each MUX is controlled to enable outputting the non-AMPI read control signal from the respective first input to the respective memory plane.