Word Line Decoding Circuit With Shared Level Conversion
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Solution Overview
Problem
Conventional word line decoding circuits require a large number of level conversion circuits, leading to increased chip area and cost in high-capacity FLASH memory chips, which hinders miniaturization and cost reduction.
Innovation Solution
A word line decoding circuit comprising multiple address decoding and level conversion modules, along with a word line toggle switch signal generation module, reduces the number of level conversion circuits by using a novel structure that generates word line signals based on low and high voltage sources, effectively minimizing the chip area and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional designs use one level conversion circuit per word line toggle switch, then each word line can be properly controlled, but the chip area increases significantly with higher capacity
Solution Approach 1:
The patent merges multiple level conversion functions into a single shared level conversion circuit. Instead of having separate level conversion circuits for each word line toggle switch, the invention uses one level conversion circuit that serves multiple word lines through shared control signals and multiplexed operation, thereby reducing the total number of level conversion circuits while maintaining proper voltage control for all word lines
Solution Approach 2:
The level conversion circuit is designed with universal functionality to handle multiple word lines. The circuit can be dynamically configured through control signals to provide appropriate voltage levels to different word line toggle switches based on which word line is currently being accessed, making a single circuit perform the work of multiple dedicated circuits
2Quantity of substance
If more word line toggle switches are used for higher capacity, then storage capacity increases, but the number of level conversion circuits increases, leading to higher cost
Solution Approach 1:
The level conversion circuit is designed with universal functionality to handle multiple word lines. The circuit can be dynamically configured through control signals to provide appropriate voltage levels to different word line toggle switches based on which word line is currently being accessed, making a single circuit perform the work of multiple dedicated circuits
Solution Approach 2:
The patent segments the control of multiple word lines into distinct control signal groups that can be independently managed. By dividing the word line selection into multiple address decoding stages (first, second, and third address decoding modules), the system can selectively activate only the necessary portion of the level conversion circuit for the current operation, reducing overall complexity
3Adaptability or versatility
If more level conversion circuits are added for higher capacity, then more word lines can be controlled, but the chip area increases, hindering miniaturization
Solution Approach 1:
The patent merges multiple level conversion functions into a single shared level conversion circuit. Instead of having separate level conversion circuits for each word line toggle switch, the invention uses one level conversion circuit that serves multiple word lines through shared control signals and multiplexed operation, thereby reducing the total number of level conversion circuits while maintaining proper voltage control for all word lines
Solution Approach 2:
The patent introduces a time dimension to the level conversion circuit operation by using dynamic control signals that switch the circuit's function over time. Instead of having spatially separate circuits for each word line, the single circuit operates in different time slots to serve different word lines, effectively adding a temporal dimension to resolve the spatial area constraint
Data Source
AI summary
A word line decoding circuit and memory comprises a first address decoding module to obtain word line logic signals; a word line pre-coding module to obtain word line pre-coding signals and first switch signals; a second address decoding module to obtain first and second selection signals; a third address decoding module to obtain third selection signals; a first level conversion module which performs level conversion on the first selection signals to obtain first and second control signals; a second level conversion module which performs level conversion on the second selection signals to get third and fourth control signals; a third level conversion module which performs level conversion on the third selection signals to obtain fifth control signals; a word line toggle switch signal generation module which generates second switch signals based on each control signal; and a word line toggle module to generate word line signals.


