Stacked High-Voltage Memory Circuit Using Core Devices
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Solution Overview
Problem
Memory circuits, including eFuse and anti-fuse, require high voltage for programming, causing voltage stress on memory peripheral circuits and arrays, leading to potential device failures due to lower breakdown voltages of core devices used in advanced fabrication nodes.
Innovation Solution
Implementing double or triple stack memory arrays and power switch circuits using core devices to withstand higher programming voltages without stress, along with level shifting and fractional voltage generation for stacked circuits, eliminating the need for I/O devices and reducing chip area and increasing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage is used for programming memory circuits, then programming capability is achieved, but voltage stress causes device failures
Solution Approach 1:
The patent divides the voltage stress burden by stacking multiple core devices in series. Each device in the stack experiences only a fraction of the total programming voltage, preventing any single device from exceeding its breakdown voltage and failing. This segmentation approach allows the circuit to withstand high programming voltages while maintaining device reliability.
2Reliability
If I/O devices are used to handle high voltage, then voltage stress on core devices is reduced, but chip area increases
Solution Approach 1:
The patent makes core devices multi-functional by enabling them to directly handle high voltage programming operations through stacking. Previously, core devices were limited to low-voltage logic operations and required separate I/O devices for high-voltage handling. Now, the same core devices can perform both logic operations and high-voltage programming, eliminating the need for dedicated I/O devices and reducing chip area.
3Productivity
If advanced fabrication nodes are used, then device density and speed are improved, but breakdown voltage decreases
Solution Approach 1:
The patent compensates for the reduced breakdown voltage of advanced node devices by stacking multiple devices in series. Each device operates within its safe voltage range, while the stack as a whole can withstand the high programming voltage required for memory operations. This allows the use of fast, high-density advanced node devices without sacrificing voltage tolerance.
Solution Approach 2:
The patent changes the voltage distribution parameter by dividing the total programming voltage across multiple stacked devices. Instead of applying the full high voltage to a single device (which would exceed its breakdown voltage), the voltage is segmented and distributed across the stack, allowing advanced node devices to operate at their optimal high speed while remaining within their voltage tolerance limits.
Data Source
AI summary
One aspect of this description relates to a memory array. The memory array includes a plurality of N-stack pass gates, a plurality of enable lines, a plurality of NMOS stacks, a plurality of word lines, and a matrix of resistive elements. Each N-stack pass gate includes a stage-1 PMOS core device and a stage-N PMOS core device in series. Each stage-1 PMOS is coupled to a voltage supply. Each enable line drives a stack pass gate. Each N-stack selector includes a plurality of NMOS stacks. Each NMOS stack includes a stage-1 NMOS core device and a stage-N NMOS core device in series. Each stage-1 NMOS core device is coupled to a ground rail. Each word line is driving a stack selector. Each resistive element is coupled between a stack pass gate and a stack selector. Each voltage supply is greater than a breakdown voltage for each of the core devices.