Multi-Stack Memory Array Circuit for High-Voltage Programming
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Solution Overview
Problem
Memory circuits, including eFuse and anti-fuse, require high voltage for programming, which puts memory peripheral circuits and arrays under voltage stress, leading to reliability concerns with core devices failing due to lower breakdown voltages.
Innovation Solution
Implementing double or triple stack memory arrays and power switch circuits using core devices to withstand higher programming voltages without stress, along with level shifting and fractional voltage generation for stacked circuits to manage biases effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage is used for programming memory cells, then programming capability is achieved, but memory peripheral circuits and arrays experience voltage stress leading to device failure
Solution Approach 1:
The circuit is divided into multiple voltage domains (first voltage domain for core devices, second voltage domain for I/O devices) with isolated power supplies. This segmentation allows core devices to operate at lower voltages while I/O devices handle high voltage programming, preventing voltage stress from propagating to sensitive core circuits.
Solution Approach 2:
A level shifter circuit acts as an intermediary between the first and second voltage domains. It translates control signals from the low voltage domain to the high voltage domain, enabling coordinated operation while maintaining electrical isolation and protecting core devices from high voltage stress.
2Reliability
If I/O devices are used for high voltage circuitry, then high voltage operation is enabled, but chip area increases
Solution Approach 1:
Core devices are designed to perform multiple functions: they serve as both the operational computing elements and as the high voltage switching elements for bit line selection. This eliminates the need for separate I/O devices, reducing chip area while maintaining high voltage operation capability through stacked core device configurations.
3Area of stationary object
If core devices are used instead of I/O devices, then chip area is reduced, but breakdown voltage is insufficient for high voltage programming
Solution Approach 1:
Multiple core devices are stacked in series to form a voltage division structure. The stacked configuration allows the combined breakdown voltage of individual core devices to withstand the high programming voltage, while each device operates within its safe voltage range. This nested arrangement enables high voltage operation using only core devices without requiring I/O devices.
Data Source
AI summary
One aspect of this description relates to a memory array. The memory array includes a plurality of N-stack pass gates, a plurality of enable lines, a plurality of NMOS stacks, a plurality of word lines, and a matrix of resistive elements. Each N-stack pass gate includes a stage-1 PMOS core device and a stage-N PMOS core device in series. Each stage-1 PMOS is coupled to a voltage supply. Each enable line drives a stack pass gate. Each N-stack selector includes a plurality of NMOS stacks. Each NMOS stack includes a stage-1 NMOS core device and a stage-N N MOS core device in series. Each stage-1 NMOS core device is coupled to a ground rail. Each word line is driving a stack selector. Each resistive element is coupled between a stack pass gate and a stack selector. Each voltage supply is greater than a breakdown voltage for each of the core devices.