Analog Neural Net FPGA Routing Using Pulse-Width Signal Encoding
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Solution Overview
Problem
Analog neural network integrated circuits face challenges in routing variable voltages due to the need for operational amplifiers, which introduce errors and consume significant power and die area, making them expensive and inflexible, while digital-analog conversions are costly and error-prone.
Innovation Solution
The solution involves converting analog quantities into analog timing pulses for routing through switch points, using a charge-to-pulse-width converter circuit and programmable Vt transistors, eliminating the need for operational amplifiers and reducing linearity requirements, and utilizing a user-programmable routing network with interconnect conductors and matrix vector multipliers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If operational amplifiers are used to buffer analog voltage levels for routing, then the analog neural network can maintain signal integrity, but the die area and static power consumption increase significantly
Solution Approach 1:
The patent extracts the buffering function from traditional operational amplifiers and implements it using simple transistor switches in an FPGA routing network. By removing the need for complex buffering circuits and replacing them with simple switching elements, the die area is dramatically reduced while maintaining signal routing capability through voltage-level translation.
Solution Approach 2:
The patent uses voltage-to-time conversion to create a temporal copy of the analog voltage signal. Instead of directly routing voltage levels which require buffering, the system converts voltages to time intervals (pulse widths), routes these time-encoded signals through the FPGA, and converts them back to voltages at the destination, eliminating the need for analog buffers throughout the routing path.
2Reliability
If operational amplifiers are used to buffer analog voltage levels for routing, then the analog neural network can maintain signal integrity, but the static power consumption increases significantly
Solution Approach 1:
The patent removes the power-hungry operational amplifier buffering stage from the signal path. By using voltage-to-time conversion and routing time-encoded signals through digital FPGA logic, the system eliminates the continuous static power consumption associated with analog buffering while maintaining signal integrity through the computational equivalence of the transformation.
Solution Approach 2:
The patent substitutes the mechanical/electrical analog buffering system (operational amplifiers) with a digital time-encoding system. The continuous analog voltage buffering is replaced by discrete time interval measurements and digital logic routing, which consumes significantly less static power while achieving the same signal transmission function.
3Adaptability or versatility
If digital-to-analog converters are used for interface conversion, then the system can interface with digital circuits, but the cost and error rate increase
Solution Approach 1:
The patent introduces voltage-to-time and time-to-voltage conversion circuits as intermediary elements between the analog neural network and digital interfaces. Instead of using complex digital-to-analog converters that introduce errors, the system uses simpler time-domain conversion that maintains accuracy and reduces interface complexity, serving as an effective mediator between analog and digital domains.
4Adaptability or versatility
If digital-to-analog converters are used for interface conversion, then the system can interface with digital circuits, but the system speed decreases
Solution Approach 1:
The patent replaces the slow digital-to-analog conversion process with faster voltage-to-time and time-to-voltage conversion mechanisms. By operating in the time domain rather than directly converting digital codes to analog voltages, the system achieves faster interface speeds while maintaining digital compatibility, effectively substituting a slower conversion mechanism with a faster temporal transformation approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces errors, power consumption, and costs by eliminating the need for operational amplifiers and digital-to-analog conversions, while maintaining the efficiency of analog computation with improved flexibility and accuracy.
Implementation Method 1
Conversion from voltage to time employs a capacitor charged to an analog voltage which capacitor is discharged by a current source and generates a pulse having a width representing the analog voltage
Implementation Method 2
capacitor is discharged by a current source and generates a pulse having a width representing the analog voltage
Implementation Method 3
generates a pulse having a width representing the analog voltage (an analog time pulse) triggered by a comparator coupled to the capacitor
Data Source
AI summary
A method for implementing a neural network system in an integrated circuit includes presenting digital pulses to word line inputs of a matrix vector multiplier including a plurality of word lines, the word lines forming intersections with a plurality of summing bit lines, a programmable Vt transistor at each intersection having a gate connected to the intersecting word line, a source connected to a fixed potential and a drain connected to the intersecting summing bit line, each digital pulse having a pulse width proportional to an analog quantity. During a charge collection time frame charge collected on each of the summing bit lines from current flowing in the programmable Vt transistor is summed. During a pulse generating time frame digital pulses are generated having pulse widths proportional to the amount of charge that was collected on each summing bit line during the charge collection time frame.