Gated Computing Memory Cells for Parallel Bit-Line Processing

The patent merges memory storage and processing functions into a single integrated structure. Memory cells store data while logic elements perform computations directly on stored data, eliminating the need to transfer data between separate memory and processing units. This combination resolves the contradiction by improving productivity through in-memory computing while reducing time cost by eliminating data movement overhead.

The patent introduces bit lines as intermediaries that enable simultaneous read operations across multiple memory cells. These bit lines serve as mediators that collect signals from multiple memory locations in parallel, allowing the system to process large amounts of data simultaneously without increasing time cost, thus resolving the contradiction between productivity and time loss.

By merging memory and processing functions into an integrated architecture where logic elements are embedded within memory cells, the patent eliminates power-consuming data transfers between separate components. Processing operations are performed directly where data is stored, improving productivity while minimizing power consumption by removing the energy overhead of data movement.

The memory system performs processing operations on its own stored data without requiring external processors. The logic elements within each memory cell enable the memory to service its own computational needs, improving productivity while reducing power consumption by eliminating the energy cost of external data transfer and processing.

The patent applies partial action by performing computations on a subset of data values directly during the read operation. Logic elements evaluate Boolean functions on selected memory cell outputs without requiring complete signal equalization across all bit lines. This approach maintains high data access speed while reducing equalization complexity by processing only the necessary portion of data.

The patent replaces the mechanical/electrical signal equalization process with logical evaluation. Instead of physically equalizing signals across bit lines through complex circuitry, logic elements directly evaluate Boolean functions on memory cell outputs. This substitution maintains high access speed while dramatically reducing equalization complexity by using logical operations rather than signal conditioning.

The patent implements multi-functionality by designing memory cells that simultaneously perform storage and processing functions. Each memory cell contains both storage elements and logic elements that can evaluate Boolean functions. This universal design improves processing efficiency by enabling in-cell computations while managing device complexity through functional integration rather than adding separate processing components.

The patent applies segmentation by dividing the processing function into discrete logic elements that are distributed across multiple memory cells. Each logic element handles specific Boolean evaluations on its associated memory cell outputs. This segmentation improves processing efficiency through parallel distributed computation while managing device complexity by breaking down the processing function into manageable modular units.