Neural Network Weight Calibration for Memory Cell Variability

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Solution Overview

Problem

Deep learning artificial neural networks face challenges in calibration due to variations among transistors, memory cells, and changes in operating temperature, which affect the accuracy and efficiency of electrical parameters.

Innovation Solution

The use of non-volatile memory arrays with continuous programming and individual tuning of memory cells, combined with calibration methods that adjust electrical parameters in real-time, such as bit resolution and temperature compensation, to maintain optimal performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If non-volatile memory arrays are used for synapses with high connectivity, then computational parallelism and energy efficiency are improved, but manufacturing precision and device variability worsen

Engineering Contradiction:

Improveenergy efficiencyVSAvoiddevice variability

Core Design Contradiction:

Use of energy by moving objectVSManufacturing precision

Solution Approach 1:

The patent implements calibration circuits that measure actual memory cell characteristics and use this feedback to adjust weighting values, compensating for manufacturing variations and maintaining accurate neural network computations despite device variability

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The system dynamically adjusts electrical parameters such as voltage levels and weighting values to compensate for manufacturing variations, allowing the neural network to maintain performance despite inconsistencies in memory cell characteristics

Inventive Principle:

Principle #35Parameter changes

2Measurement precision

If individual tuning of memory cells is performed to compensate for variations, then measurement precision is improved, but device complexity and calibration time worsen

Engineering Contradiction:

Improveweight value accuracyVSAvoidcalibration circuit complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The patent combines multiple calibration functions into integrated calibration circuits that perform measurement, adjustment, and compensation operations simultaneously, reducing overall system complexity while maintaining precision

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The calibration circuits are designed to handle multiple memory cells and various types of variations using unified measurement and adjustment mechanisms, reducing the need for separate calibration paths for each cell

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Reliability

If real-time calibration is performed to compensate for temperature changes, then reliability is improved, but use of energy and processing time worsen

Engineering Contradiction:

Improvenetwork accuracyVSAvoidcalibration energy consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The system performs calibration operations periodically or at predetermined intervals rather than continuously, reducing energy consumption while maintaining reliability by updating parameters at appropriate intervals during temperature changes

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The patent implements preliminary calibration operations during manufacturing or initialization to establish baseline characteristics, reducing the need for frequent real-time calibration and thereby lowering ongoing energy requirements

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS20230252276A1Calibration of electrical parameters in a deep learning artificial neural network

Publication Date: 2023.08.10 SILICON STORAGE TECHNOLOGY INC

AI summary

Numerous examples are disclosed for performing calibration of various electrical parameters in a deep learning artificial neural network. In one example, a system comprises a digital-to-analog converter for receiving an input of k bits and generating a first analog output, a mapping scalar for converting the first analog output into a second analog output, and an analog-to-digital converter for generating an output of n bits from the second analog output, where n is a different value than k.