Crossbar Array Programming With Grounded Columns to Limit Sneak Currents
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Solution Overview
Problem
Crossbar array circuits face challenges in reducing signal disturbances such as static sneak current and dynamic sneak current, which can lead to accidental programming of devices and performance degradation, especially as the size of the array increases.
Innovation Solution
The design includes a crossbar array circuit with a plurality of rows and columns, where devices are connected to shared ends that are grounded or hold a stable voltage potential, and a method of programming that involves selecting a target device, grounding the target column, and sending a pulse signal through an access transistor to minimize sneak currents. Additionally, un-selected rows are pre-charged with a voltage potential of the same polarity as the programming signal to reduce dynamic sneak current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If crossbar array circuits are used for memory and computing applications, then high integration and parallel processing capability are achieved, but signal disturbances such as static sneak current and dynamic sneak current increase
Solution Approach 1:
The crossbar array is segmented into multiple independently controllable blocks or regions. Each block can be programmed or read independently with its own set of word lines and bit lines, isolating the sneak current effects to local regions rather than affecting the entire array. This maintains high integration while reducing signal disturbance through spatial segmentation.
Solution Approach 2:
Additional intermediary lines or structures are introduced between the main word lines and bit lines to control and suppress sneak currents. These intermediary elements act as mediators that can selectively enable or disable current paths, preventing unwanted current leakage while maintaining the parallel processing capability of the crossbar array.
2Quantity of substance
If array size is increased to improve capacity and performance, then more devices can be integrated, but sneak current becomes more severe
Solution Approach 1:
Large crossbar arrays are divided into smaller sub-arrays or blocks that can be independently addressed and controlled. This segmentation limits the propagation distance of sneak currents within each block, reducing their magnitude even as the total array capacity increases. Multiple blocks can be activated simultaneously to maintain high throughput.
Solution Approach 2:
The array architecture is extended into additional dimensions through multi-layer stacking or three-dimensional crossbar structures. This allows increased device capacity without proportionally increasing the planar area, and the vertical dimension provides additional control points for suppressing sneak currents through selective grounding or voltage application on intermediate layers.
3Speed
If conventional programming methods are used, then programming speed is maintained, but accidental programming of non-target devices occurs due to sneak current
Solution Approach 1:
Before programming a target device, preliminary actions are taken to prepare the array state: non-target word lines are pre-charged to appropriate voltages, and non-target bit lines are pre-discharged or grounded. This preliminary preparation ensures that when the programming pulse is applied, sneak current paths are already suppressed, preventing accidental programming while maintaining fast programming speed.
Solution Approach 2:
The programming scheme incorporates feedback mechanisms where the state of bit lines and word lines is monitored during programming operations. Based on this feedback, additional control pulses are applied to suppress emerging sneak currents in real-time, ensuring programming accuracy is maintained even at high speeds. The feedback loop dynamically adjusts control signals to prevent off-target device programming.
Data Source
AI summary
Crossbar arrays with reduced disturbance and methods for programming the same are disclosed. In some implementations, an apparatus comprises: a plurality of rows; a plurality of first columns; a plurality of second columns; a plurality of devices. Each of the plurality of devices is connected among one of the plurality of rows, one of the plurality of first columns, and one of the plurality of second columns. The device further comprises a shared end on the plurality of first columns or the plurality of the second columns connecting to the plurality of the devices in the same row or column; the shared end is grounding or holds a stable voltage potential. In some implementations, one of the devices is: a RRAM, a floating date, a phase change device, an SRAM, a memristor, or a device with tunable resistance. In some implementations the stable voltage potential is a constant DC voltage.