Memory Clock Mode Configuration for Serial Ring Topology
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Solution Overview
Problem
The existing flash memory systems face performance limitations due to signal integrity issues such as crosstalk, signal skew, and simultaneous switching noise, as well as increased power consumption with higher system clock frequencies, when multiple memory devices are connected in parallel, limiting the number of devices that can be effectively used.
Innovation Solution
A serially connected memory system with a ring topology configuration, where memory devices are connected serially with each other and the memory controller, allowing for the use of either parallel or serial clock signals, and a configurable clock mode circuit that enables operation in both parallel and serial clock modes, optimizing data transfer rates and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory devices are connected in parallel to increase storage capacity, then the available storage capacity increases, but signal integrity is degraded by crosstalk, signal skew, and simultaneous switching noise
Solution Approach 1:
The patent segments the memory system into multiple channels, with each channel connecting to a subset of memory devices. This segmentation reduces the number of devices per channel, thereby improving signal integrity while maintaining total storage capacity through parallel channel operation.
Solution Approach 2:
The patent introduces a memory controller as an intermediary that manages multiple channels and devices. The controller coordinates access across channels, enabling the system to scale storage capacity while maintaining signal integrity through controlled signal paths.
2Productivity
If system clock frequency is increased to improve data transfer rate, then the data transfer rate increases, but power consumption increases
Solution Approach 1:
The patent implements dynamic clock gating that selectively enables or disables clock signals to individual memory devices based on operational requirements. This dynamic approach allows the system to achieve high data transfer rates when needed while reducing power consumption during idle or low-demand periods.
3Quantity of substance
If the number of memory devices connected in parallel increases to accommodate large memory systems, then the memory capacity increases, but the drive capability becomes insufficient due to loading on long signal tracks
Solution Approach 1:
The patent divides the memory system into multiple channels, each handling a manageable subset of devices. This segmentation ensures that signal tracks remain short enough to maintain drive capability while the aggregate capacity of all channels provides the required total memory capacity.
4Quantity of substance
If more chip enable signals are required to control additional memory devices, then the number of addressable devices increases, but the device complexity increases
Solution Approach 1:
The patent designs the memory controller with universal chip enable signals that can address devices across multiple channels. This multi-functional approach allows a limited set of control signals to manage a large number of devices, reducing overall system complexity while maintaining expandability.
Data Source
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Figure 2A~2B
Figure 3A
AI summary
A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.